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Raspberry Pi Forum The Raspberry Pi 5 has a new Chip - The RP1 has a Secret
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Forum Thread Details
  • Replies 9 replies
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  • RP1
  • microprocessor
  • cortex-m3
  • raspberry pi 5
  • programmable input output
  • rp2040
  • microcontroller
  • PIO
Related

The Raspberry Pi 5 has a new Chip - The RP1 has a Secret

cstanton
cstanton over 1 year ago

Those of you who are familiar with desktop or laptop computers will already be familiar with "northbridge" and "southbridge" types of chips. These are common on motherboards these days and compliment the central processing unit and graphics processing unit in your computer.

Usually, a northbridge chipset handles integration between CPU, PCI-E and RAM devices, where as the southbridge communicates with the northbridge and any further, external or legacy or basic components. Such as USB, ISA, BIOS, PCI, IDE, etc.

The Raspberry Pi 5 integrates a southbridge chip, the RP1.

Not a great deal is known about this chip yet, the datasheets haven't been fully revealed or distributed, however there have been some discussions about it in various places by the engineers from Raspberry Pi, and Luke Wren has something to say about its capabilities:

image

If you're unable to read the image it says:

"There is one PIO instance (4 state machines). It's identical to the PIO blocks on RP2040, except the FIFO depth is doubled. It has single-cycle bus access from the dual Cortex-M3 management processors on RP1, and the PIO FIFOs can also be accessed from the host processor (2712) over PCIe, but the PIO configuration registers are only accessible to the RP1 processors.

One of RP1's Cortex-M3s is currently going spare, so it should be possible to write your own Cortex-M firmware and load it into the 16 kB per-Cortex-M3 private SRAM. There won't be any software support for this at launch though."

Luke further elaborates on this on X / Twitter:

I want to walk back that point about PCIe access to FIFOs. The PIO block's AHB port is connected to RP1's processor fabric, and we added a second bus interface which exposes (just) the FIFOs to RP1's system bus fabric, so that RP1's internal DMA can access the FIFOs. This ...

— Luke Wren @wren6991@types.pl (@wren6991) September 29, 2023

... does also expose them over PCIe, since there is a route from 2712's PCIe windows through to the top of RP1's system fabric, but this is not actually usable for host transfers since you can't access the status registers.

Using RP1's PIO requires firmware running on RP1.

— Luke Wren @wren6991@types.pl (@wren6991) September 29, 2023

But yeah, there's a PIO block in there, we're putting that bad boy in everything from now on

— Luke Wren @wren6991@types.pl (@wren6991) September 29, 2023

It would appear that we have another microprocessor to play with! Though for most it will not be a trivial component to handle, and there's no software support for it (just yet). Perhaps those of you that were hoping for an embedded RP2040 can play with this instead?

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  • Fred27
    Fred27 over 1 year ago

    I'm looking forward to exploring the PIO on the Pi 5. I think it opens up a lot of real-time capability. However, I wonder whether it's worth waiting until there's a bit of official support and documentation though, I suspect it could be quite tricky to work with unless you have a bit of insider guidance.

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  • misaz
    misaz over 1 year ago in reply to Fred27

    the hard part is that it is from main SoC accessible over PCIe. I think it will work in a way that you build firmware for Cortex-M3, this firmware you need to upload somehow over PCIe to the RP1 and using this firmware you can control the PIO. The most confusing currently seems to be the proprietary PCIe path.

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  • cstanton
    cstanton over 1 year ago in reply to Fred27
    Fred27 said:
    the PIO on the Pi 5

    Y'know I admit, I keep seeing PIO mentioned, but I don't see explanations of it and how to use it, have I missed some obvious resource? Likely about the RP2040?

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  • Fred27
    Fred27 over 1 year ago in reply to cstanton

    That's the thing. Some info has come out about the fact that there is a PIO within the RP1 (and an unused Cortex-M3). There is no info about how you could use it yet.

    I suspect it was dropped in because it was reasonably easy to do at minimal cost and it is likely to be useful later. Maybe some official documentation will come. Maybe the large and enthusiastic Pi community will find a way beforehand. Some interesting stuff ahead.

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  • beacon_dave
    beacon_dave over 1 year ago in reply to Fred27
    Fred27 said:
    Maybe some official documentation will come.

    Or perhaps wait for the upcoming movie...

    "We’re going to be doing an in-depth video about RP1 here some time over the next few weeks: watch this space."

    https://www.raspberrypi.com/news/introducing-raspberry-pi-5/#comment-1594555

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  • baldengineer
    baldengineer over 1 year ago

    I certainly hope these details point towards an addition to the microcontroller family.

    Larger FIFO on the PIO and Cortex-M3 would make for an interesting RP2040 follow on.

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  • cstanton
    cstanton over 1 year ago in reply to Fred27
    Fred27 said:
    That's the thing. Some info has come out about the fact that there is a PIO within the RP1

    Thanks for the response, however, that didn't answer my question, perhaps I did not phrase it properly?

    PIO is apparently "Programmable Input Output", I did not realise this is covered in Chapter 3. of the RP2040 datasheet: 

    https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf 

    Adafruit (of course...) have an introduction on it with CircuitPython:

    https://learn.adafruit.com/intro-to-rp2040-pio-with-circuitpython/overview 

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  • Fred27
    Fred27 over 1 year ago

    Just spotted on Haskster.io that a draft datasheet for the RP1 is available. Here's a direct link to the PDF.

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  • shabaz
    shabaz over 1 year ago in reply to Fred27

    Nice, was discussing with a friend the other day, we predicted that this would happen! (that they might eventually sell it, or make it available to customers adding Pi 5 into their products).

    Fairly sure that this would be perfect for industrial customers. Now those customers can implement more Ethernet interfaces, more USB, etc on the Pi 5 whenever they feel like it! Whether it's for more throughput, or for routing, or even redundancy!

    It would even be possible to have hot-swappability on those interfaces. Possibly extreme for consumer stuff, but perhaps some customers demand that too!

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