Raspberry Pi Pico 2 and a new micro-controller with RISC-V and Arm?

May be its a trial run for a future RISCV only SoC. May be Pico3 be an exclusive RISCV CPU!

I'm going to say it:

Risk architecture (like many these days) only matters to 

• controller manufacturers that have to pay a per-chip license to ARM, and
• assembler language developers that do a better job than the GCC / Lang toolchain developers

And also feels like quite a hostile move against ARM. They can't surely be happy about it. I'm guessing there's zero revenue payable to ARM unless the cores are actually used (well, made available to customers to access), and now it's in raspberrypi.com control to turn off that license fee tap if they want, by just programming the register to disable the cores.

Also, wondering just out of curiosity does anyone know if that's the only third-party IP in the chips, or if rasperrypi.com also pay fees for anything else in the chip? 

3.9.2. Mixed Architecture Combinations :
The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1

They even pay fees for standard peripherals like I2C driver. In this particular case, I2C controller is licenced from synopsys. Majority of this chip is just bought elsewhere. It is quite common nowadays.

CPU architecture affect much more and one more reason is: perfromance. While for some embedded application it does not matter much, nowdays we see increased usage of AI/ML models on MCU and in that case perofrmance is very important and it really matter if your AI model run 5 times faster on the same clock rate just because instruction set is more optimized for these applications.

I thought that vendors will go Maxim way that integrates HW accelerator and optimized DMA for accelerating loading data, coeficients, and do ccomputations in HW accelerated and highly paralelised way, but it seems that most other vendors go by increasing clock rate and optimizing instruction set (ARM Cortex-M35, 55, 85) for these applications instead.

I was going to ask how you knew that, if there was a list, but just noticed that the RP2040 documentation (RP2040 PDF datasheet) contains it. 

Easiest way is to search for the text "used with permission" and the IP is discovered, summarized here:

• UART: ARM PrimeCell
• I2C: Synopsys
• SPI: ARM PrimeCell
• SSI: Synopsys

The only difference with RP2350 PDF datasheet, is that the latter does not mention Synopsis for the IP for SSI (used for the QSPI interface in the RP2040, for the Flash memory).

I thought that the i2c fees expired in the earlier 2000s ...

It is not fee for a I2C licence. It is fee for a licence for a VHDL/Verilog implementation of controller.

I don't know how well the Risk 5 competes with ARM M33, clock for clock or watt for watt. And there may well be big performance differences between different manufacturers implementations of the same cores.

I've been working a project using the ST32MU575 (Cortex M33 like the Pico 2350) and the interesting thing about this chip is how much of it is devoted to peripherals. It costs more than the 2350 but totally blows it away in terms of on chip peripheral support. Partly as an experiment, but for some other reasons too,  I have chosen to implement quite a complex project without using interrupts at all. This is possible on the 'U575 because of the sophisticated timers and the complex linking possible between timers, the two ADCs (1  is 14 bit)  and the USARTS etc. The DMA is pretty flashy too, offering a linked list architecture which can do amazing stuff once your brain gets over the shock !

I'd really like to see some some comparisons between the different cores on the 2350 because I think Jan may be right, but with the additional caveat that its (often) what surrounds the core that matters.

(Oh, and don't forget tool and debugging support !)

MK