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  • basys-3
  • fpga
  • vga
Related

Clock problems on Basys 3

nixiefairy
nixiefairy over 7 years ago

Hey everyone!

I have been busy working on the roadtest of Basys 3 entry level board for a few days now. Recently, I got stuck while implementing one of the projects.

I am trying run a snake-apple game on the Basys 3 using a VGA input monitor. Thing is I am getting an error saying that my refresh rate is incorrect. For a 640X580 display, pixel rate has to be close to 25Mhz. Even after setting up the frequency of the display, I am still hitting a wall. Any suggestions? Codes and error attached below (vga_tst is top module):

Attachments:
codes.zip
image
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  • michaelkellett
    michaelkellett over 7 years ago +2 suggested
    What is the pixel frequency, and how are you controlling it. (BTW, is it 640 x 480 ?) The FPGA has a pll so you may need to use that to make a clock frequency which can be divided by a suitable integer…
  • michaelkellett
    michaelkellett over 7 years ago in reply to nixiefairy +1 suggested
    Here's a useful link: http://martin.hinner.info/vga/timing.html Run a simulation of you design and check that the signals look right. Does your design meet timing constraints in the Xilinx tools. Then…
  • gecoz
    gecoz over 7 years ago +1 suggested
    Hi Eashan, I only had a quick look, but noticed in your code you use a mod-2 counter to generate the 25MHz pixel tick, which implies a 50MHz clock reference, but if you are using the Basys 3 reference…
  • michaelkellett
    0 michaelkellett over 7 years ago

    What is the pixel frequency, and how are you controlling it. (BTW, is it 640 x 480 ?)

     

    The FPGA has a pll so you may need to use that to make a clock frequency which can be divided by a suitable integer to make  a pixel clock.

     

     

    The Xilinx tools can help you set up the PLL.

     

    MK

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  • nixiefairy
    0 nixiefairy over 7 years ago in reply to michaelkellett

    Hey Michael,

    Thanks for the reply! I actually am using the PLL, to generate a 25Mhz clock (for driving the VGA).

    My issue is the error which is showing up in the monitor. I mean what frequency should I use, if 25Mhz is not the correct one? I want the display to be working properly.

    (Sorry meant 640X480, typo, thanks!)

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  • michaelkellett
    0 michaelkellett over 7 years ago in reply to nixiefairy

    Here's a useful link:

     

    http://martin.hinner.info/vga/timing.html

     

    Run a simulation of you design and check that the signals look right. Does your design meet timing constraints in the Xilinx tools.

     

    Then check (using a scope) that the signals your physical design makes look OK.

     

    MK

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  • gecoz
    0 gecoz over 7 years ago

    Hi Eashan,

     

    I only had a quick look, but noticed in your code you use a mod-2 counter to generate the 25MHz pixel tick, which implies a 50MHz clock reference, but if you are using the Basys 3 reference clock, this is a 100MHz, not a 50MHz, so you would need a mod-4 counter instead. Using a mod-2 counter, you would end up with a refresh rate of 120Hz, which would explain why your monitor is complaining.

     

    Fabio

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  • nixiefairy
    0 nixiefairy over 7 years ago in reply to gecoz

    Sadly didn't work out...Will try out Michael's debugging strategy. Thanks!

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  • nixiefairy
    0 nixiefairy over 7 years ago

    Okay so I got the solution to the problem : It was wrong implementation of the clock of the clock divider module. I've written a new one which can be used by the community for dividing their clock. Feel free to use it.

    module newClk(

    input master_clk,

    output reg op_clk,

    input num);

                                                  //usage: masterclk=100Mhz(say) so for op_clk=25Mhz, num should be num=4

    integer x=0;

    always@ (posedge master_clk)

    begin

    x<=x+1;

        if(x==num)

            begin

            op_clk<=~op_clk;

            x<=0;    

    end

    else

    op_clk<=op_clk;

    end

    endmodule

    Thanks everyone for your input!

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  • michaelkellett
    0 michaelkellett over 7 years ago in reply to nixiefairy

    I'm not a frequent user of Verilog but I don't think you need this last bit, op_clk is a reg so will keep its value - so you only need to drive it when it changes.

     

    else

    op_clk<=op_clk;

    end

     

     

     

    You may have issues with simulation because op_clk is undefined at start up so ~op_clk is undefined, so op_clk is always undefined. In hardware this doesn't matter - it must start up as something but the simulator may not see it that way.

     

    If you want op_clk defined as you come out of reset then you need a reset input to your module and to use that to pre-set op_clk.

     

    Xilinx argue strongly against resetting everything.

     

    Google ' xilinx synchronous reset verilog' to learn more than you ever thought possible about resets !

     

    MK

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  • gecoz
    0 gecoz over 7 years ago in reply to nixiefairy

    Hi Eashan,

     

    Glad to hear you managed to solve the problem. I see now you have implemented a generic module-"num" counter. For the Basys 3 , have you used the 100MHz reference clock with mod-4 counter then? I'm asking because in your previous reply to my suggestion, you said that solution it didn't work, so I'm curious to know what worked.

     

    fabio

     

     

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  • nixiefairy
    0 nixiefairy over 7 years ago in reply to michaelkellett

    Hey Michael,

     

    1) I am leaving op_clk<=op_clk cause you just don't know how it effects an FPGA. Better to have a safe run than having an error!

    2) Fair point on initializing op_clk. To be honest, I really didn't simulate it, other than using the ILA occasionally.

    3) I am leaving the clock signal asynchronous to the reset for the time being.

    Thanks for all the input you have given!

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  • nixiefairy
    0 nixiefairy over 7 years ago in reply to gecoz

    Hey Fabio,

    Yeah it was a great relief to finally have it working. I have put the project results in my review: FPGA Essentials: Basys 3 Artix-7 FPGA - Review .

    For my project I've used a 50Mhz signal coming from the FPGA. This was then passed to a clock divider module which then gave a 25Mhz clock signal. So yes, I used it as a mod-2 counter.
    It was something to do with the previous lines of code I was using.

     

    reg pixel_reg;

    wire pixel_next, pixel_tick;

     

    always @(posedge clk)

      pixel_reg <= pixel_next;

     

    assign pixel_next = ~pixel_reg; // next state is complement of current

     

    assign pixel_tick = (pixel_reg == 0); // assert tick half of the time

     

    Probably I didn't instantiate a separate module? Or probably I called this where my VGA sync signals were generating, I am not entirely sure.

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