Roadtest Product Review of AMD Kria KV260 Review by digital Pat

Table of contents

RoadTest: AMD Xilinx Kria KV260 Vision AI Starter Kit

Author: digital_pat

Creation date:

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: Nvidia Jetson Orin

What were the biggest problems encountered?: Tutorial did not have complete information on how to change the part of the design I wanted to change.

Detailed Review:

The out of box impression for the Kria KV260 was that I had everything I needed to get the board up and running.  Of course my experience included the Kria development kit and the accessory kit. So I had the som module, carrier board, power cord, SD card and cables as shown in the diagram below.

This product is incredibly powerful.  The K26 SOM has a quad core A53 with integrated FPGA fabric with ~250,000 logic elements.  The processing system connects to the programmable logic through streaming or memory mapped AXI buses. This means that the A53 cores and the FPGA have the same fast access to the memory resources.  The FPGA logic is extremely flexible and Xilinx provides 4 flavors of platforms that take advantage of this resource.  The user is also allowed to modify the FPGA logic to create a custom platform for a specific need.

Here is a block diagram of the K26SOM with only Connector 1 since Connector 2 is not supported on the KV260 Carrier board.  Also the eMMC is removed since this part is not placed on the shipped hardware.  This diagram highlights the direct connections between the programmable logic, the processing system, and the system DDR.

The Next diagram shows the peripherals connected to the SOM on the KV260 Carrier board.  

I followed the getting started guide and went with the Ubuntu option. The guide had me install the 22.04 version of Ubuntu. Unfortunately, I was not able to complete the boot. My board had a version of firmware that does not work with this version of Ubuntu. There was a note that pointed me to a wiki to address this issue. I ended up downloading the 21.04r version of Ubuntu to be able to boot; then I could update by following the wiki directions (sudo was needed on Ubuntu). All I had to do was update the firmware and I was able to follow the getting started guide from there.  I think there is a better way by accessing the web interface of the update utility, but I ended up downloading many more gigs of images and got it running.  I would have preferred clear directions instead of a note pointing to a wiki for the getting started guide.

Here are the general steps I performed to get a clean boot:

  • Download and burn Ubuntu for Kria 22.04
  • Connected everything
  • Started putty and initiated boot
  • Putty showed the boot process, but never completed due to the Firmware incompatibility.

  • After consulting the Wiki, I decided to boot an older version of Ubuntu to provide a platform to update the firmware.
  • Download and burn Ubuntu for Kria 20.04
  • Connected everything
  • Started putty and initiated boot
  • This time boot worked 
  • Download Firmware update 3 from Wiki
  • Used scp to copy it to target
  • Added Xilinx configuration with the following command
    • sudo snap install xlnx-config --classic --channel=1.x
  • Updated firmware:
    • sudo xmutil bootfw_update -i boot.bin
  • to verify:
    • sudo xlnx-config --xmutil bootfw_status
  • reboot
    • sudo xlnx-config --xmutil bootfw_update -v
  • to verify:
    • sudo xlnx-config --xmutil bootfw_status
  • Burned the Ubuntu for Kria 22.04 image
  • Now I was able to boot with the correct version of Ubuntu!
  • Added Xilinx configuration with the following command
    • sudo snap install xlnx-config --classic --channel=2.x
    • xlnx-config.sysinit
    • sudo reboot

I ended up starting with the smartcam example application.  The directions to run this application are here.  Please note that the directions are version dependent; links to the version are on the left sidebar.  

  • sudo xmutil desktop_disable
  • sudo xmutil listapps
  • sudo xmutil unloadapp
  • sudo xmutil loadapp kv260-smartcam
  • sudo add-apt-repository ppa:xilinx-apps
  • sudo add-apt-repository ppa:ubuntu-xilinx/sdk
  • sudo apt update
  • sudo apt upgrade
  • sudo apt-get install    ca-certificates    curl    gnupg    lsb-release
  • sudo mkdir -p /etc/apt/keyrings
  • curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo gpg --dearmor -o /etc/apt/keyrings/docker.gpg
  • echo  "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.gpg] https://download.docker.com/linux/ubuntu \

$(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null

  • sudo apt update
  • sudo apt-get install docker-ce docker-ce-cli containerd.io docker-buildx-plugin docker-compose-plugin
  • sudo docker run hello-world
  • sudo groupadd docker
  • sudo usermod -a -G docker  $USER
  • sudo apt install xrt-dkms
  • sudo xmutil      desktop_disable
  • sudo xmutil unloadapp
  • sudo xmutil loadapp kv260-smartcam
  • docker pull xilinx/smartcam:2022.1
  • docker run \

--env="DISPLAY" \

-h "xlnx-docker" \

--env="XDG_SESSION_TYPE" \

--net=host \

--privileged \

--volume="$HOME/.Xauthority:/root/.Xauthority:rw" \

-v /tmp:/tmp \

-v /dev:/dev \

-v /sys:/sys \

-v /etc/vart.conf:/etc/vart.conf \

-v /lib/firmware/xilinx:/lib/firmware/xilinx \

-v /run:/run \

-it xilinx/smartcam:2022.1 bash

  • This last command starts a docker container and provides a prompt
  • In docker container:
    • smartcam --mipi -W 1920 -H 1080 --target rtsp
  • On my PC, I started a VNC session and opened the network interface provided after the smartcam command was run on the target.



Please note that Ubuntu does not have USB  WiFi support for this board. This required being close enough to a router to connect to the internet. Support for USB WiFi can be compiled, but that is not part of the official version.  Between the firmware mismatch and the lack of WiFi, it took me about three hours to get the smart cam application up and running.  Much of this time was waiting on large images to download.  

Application development:

Next I started research to perform my application development. For this road test my plan is to modify the smart camera application to use an RTSP stream for both input and output. The SOM offers hardware acceleration for the encoding and decoding of video streams. Currently the smart camera application only encodes an RTSP stream for the output.  To enable decoding, I figured I need to modify the VCU module in the platform. This is done with the Vivado tool that comes with Xilinx Vitis. 

Tool Install:

To install Vitis, you NEED ~300GB of disk space and a computer that can handle some serious number crunching.  I installed Vitis 2022.1.  The installer is 70GB so it takes a while to download.  This is a tool that should be run in a native operating system; No WSL, containers, virtual machines.  That is unless you have a system with a ton of resources.  

SmartCamera Application Tutorial:

Create a Platform

I started with the tutorial to create a platform on the Smart Camera application page.  Once I pulled the Git repo, I found a make flow that called a tcl script to build the project.  I did have to add a parameter make platforme command to limit the number of threads called JOBS after my terminal window died for lack of memory resources.  My system has 16GB of ram with an 11 GB swap.  Although this method did work and I was able to open the project in Vivado to modify, I was disappointed that AMD Xilinx did not use the Open Example Project menu option in Vivado.  I would second this sentiment for the Vitis project.  Here are the steps I performed:

When you open the project in Vivado, the source window The block diagram is listed as a source under a wrapper source file..  You can open the block diagram by double clicking on the block diagram name.  

In the block diagram you can see the Zynq UltraScale+ Processor and the elements implemented in the FPGA fabric.  One of the modules in the FPGA is the VCU Logic Core.  If you double click on that block, a sub-block diagram opens as you can see below.  

Here you can click on the VCU_0 block to open a window that allows you to modify the IP.  

Here I planned to enable both the Encoder and Decoder; only to find that the platform already had what I needed! So I did not have to modify the platform for my current application.

Create Vitis Project

Next I continued the tutorial to create the Vitis project and then Integrate the Accelerator Overlay.  Here are the steps:

  • cd [WORKING DIRECTORY]
  • make platform PFM=kv260_ispMipiRx_vcu_DP JOBS=2

Integrate Accelerator Overlay

  • make overlay OVERLAY=smartcam JOBS=2

After completing the steps on the tutorial, I found myself wondering now what.  I tried to open the Vitis project and did not have success; I did not feel like I had all that I needed to move forward at this point.  Also the smart camera applications source code was nowhere to be found on my system.

Vitis tutorial for Kria KV260

So I decided to work on a general Vitis tutorial for the Kria KV260.  This tutorial was included on the github document page for the 2021.1 version of the tools and has since been removed.  Here you build a Vivado project from scratch.  This material talked about the four steps to application development:

  1. Platform hardware creation in Vivado. It exports an XSA file with clock, reset, AXI interface and interrupt signals and properties.
  2. Platform software preparation with PetaLinux, including Linux kernel, rootfs, device tree and boot components.
  3. Platform creation in Vitis to combine all hardware and software components and generate XPFM description.
  4. Create applications in Vitis against the platform. Vitis generates the host application, xclbin and sd_card.img.

I felt the Smart Camera Application tutorials covered much of steps 1-3.  The fourth step is the area I am interested in performing.  The Vitis tutorial did show me what I was missing with the smart camera project. Please note that I used the 2021.1 version of this tutorial for 2022.1 Vitis install; the latest version of this tutorial has not been updated.

Create Hardware Platform and XSA File

For this step we created a Vivado project for the KRIA KV260 board and then created a block diagram to describe the hardware around the Zynq Ultrascale+ processing system.

    • source [Vitis Install Directory]/Vitis/2022.1/settings64.sh
    • vivado &

  • File -> Project -> New

      • Enable Extensible Vitis Platform Then hit Next
      • Target the board “Kria KV260 Vision AI Starter Kit” , Name it “system”, Hit OK
    • Open Block Diagram
      • Add Zynq UltraScale+ MPSoC IP
        • Configure AXI Masters
          • Enable AXI HPM0 LPD with a data width of 32
          • Disable AXI HPM0 FPD and AXI HPM1 FPD
        • Configure Zynq PS Clocks
          • CLK1: 100
          • CLK2: 200
          • CLK3: 400
        • Add AXI Interrupt Controller 
          • Set  Interrupt Output Connection to Single
        • Run Run Connection Automation 
          • Connect axi_intc_0.s_axi to AXI HPM0 LPD

  • Connect sclk to CLK2

        • Connect IRQ port
          • Connect axi_intc_0.irq to zynq_ultra_ps_e_0.pl_ps_irq[0:0]
        • Configure Platform(on Platform Tab)
          • Enable intr under axi_intc_0
          • Enable M_AXI_HPM0_FPD and M_AXI_HPM1_FPD
          • Enable M01_AXI - M07_AXI
          • Enable S_AXI_HPC0_FPD, S_AXI_HPC1_FPD, S_AXI_HP0_FPD, S_AXI_HP1_FPD, S_AXI_HP2_FPD, S_AXI_HP3_FPD.
          • Set modport for the S_AXI_HPC0_FPD, S_AXI_HPC1_FPD  to S_AXI_HP 
          • Rename to HPC0, HPC1, HP0, HP1, HP2, HP3

      • Validate design
      • Create a wrapper for the block diagram
        • In Source list, right click on system.bd and select Create HDL Wrapper…
          • Check the option to let Vivado manage
      • Generate Block Diagram
        • Click on Generate Block Design in the Flow Manager (On the left)
          • Set Synthesis to Global.
      • Generate bitstream
        • Click on Generate Bitstream in the Flow Manager
      • Export Hardware Platform
        • File -> Export -> Export Platform

      • Set type to Hardware

          • Set Platform state to Pre-Synthesis
          • Include bitstream
          • Set properties to:
            • Name: kv260_custom_platform
            • Vendor: xilinx
            • Board: kv260
            • Version: 0.0
            • Description: This platform provides high PS DDR bandwidth and three clocks: 100MHz, 200MHz and 400MHz.
          • Set filename to kv260_custom_platform.xsa

        Create Software Platform 

        I did have to download a BSP for the Kria KV260 board and also the petalinux install to complete the steps.

        • Download the Kria KV260 BSP for 2022.1 from Here
        • Download and instal Petalinux 2022.1 development environment from Here
        • ./petalinux-v2022.1-04191534-installer.run --dir <INSTALL_DIR> --platform "arm aarch64"
        • source <petaLinux_tool_install_dir>/settings.sh
        • petalinux-upgrade -u 'http://petalinux.xilinx.com/sswreleases/rel-v2022/sdkupdate/2022.1_update1/' -p 'aarch64'
        • petalinux-create --type project -s xilinx-kv260-starterkit-v2022.1-05140151.bsp
        • cd xilinx-k26-starterkit-v2021.1
        • petalinux-config --get-hw-description=<vivado_design_dir> --silent
        • petalinux-config -c rootfs
        • Go to Filesystem packages -> libs -> xrt
        • Enable XRT
        • petalinux-build
        • petalinux-build --sdk
        • Create Device Tree Overlay
        • git clone https://github.com/Xilinx/device-tree-xlnx
        • cd device-tree-xlnx
        • git checkout xlnx_rel_v2022.1
        • xsct
        • Create file gen_dt.tcl with this in in it:
        • hsi open_hw_design <design_name.xsa>
        • hsi set_repo_path <path to device-tree-xlnx repository>
        • hsi create_sw_design device-tree -os device_tree -proc psu_cortexa53_0
        • hsi set_property CONFIG.dt_overlay true [hsi::get_os]
        • hsi set_property CONFIG.dt_zocl true [hsi::get_os]
        • hsi generate_target -dir <desired_dts_filename>
        • hsi close_hw_design [hsi current_hw_design]
        • xsct gen_dt.tcl
        • dtc -@ -O dtb -o pl.dtbo pl.dtsi

        I got the following warnings when running petalinux-build:

        WARNING: Host distribution "ubuntu-22.04" has not been validated with this version of the build system; you may possibly experience unexpected failures. It is recommended that you use a tested distribution.

        And

        WARNING: Your host glibc version (2.35) is newer than that in uninative (2.34). Disabling uninative so that sstate is not corrupted.

        For now I ignored these knowing that I may have issues in the future.  I did not experience issues related to this for this evaluation.

        Create Vitis Platform

        • mkdir kv260_custom_pkg
        • cd kv260_custom_pkg
        • mkdir pfm
        • cd <petalinux Install>/images/linux
        • ./sdk.sh -d <kria_project directory>/kv260_custom_pkg
        • cd  <kria project directory>/kv260_custom_pkg/pfm
        • mkdir boot
        • mkdir sd-card
        • cd  <kria project directory>/kv260_custom_pkg
        • vitis &
        • Select kv260_custom_pkg as working directory
        • File > New > Platform Project
          • Name project kv260_custom
          • Point to XSA file generated in step 1
          • Set the operating system to linux.
          • Set the processor to psu_cortexa53.
          • Architecture: 64-bit
          • Uncheck option Generate boot components because we will use PetaLinux generated boot components.
          • Click Finish
        • Click on  linux on psu_cortexa53 to bring up properties dialog
          • Use pull down menu to generate BIF file 
          • Set Boot Components Directory to kv_custom_pkg/pfm/boot
          • Set FAT32 Partition Directory to kv_custom_pkg/pfm/sd-card
        • Select kv260_custom Project in Explorer window
          • Click on Build icon

        Create Application

        • In Vitis kv_260_custom platform project, File -> New -> Application Project
          • Set kv260_custom as the platform
          • Name the project vadd
          • Set the domain to  linux on psu_cortexa53
          • Set Sys_root path to <kria project directory>/kv260_custom_pkg//sysroots/cortexa72-cortexa53-xilinx-linux
          • Set Root FS to <kria project directory>/kv260_custom_pkg/kv260_custom_plnx/images/linux/rootfs.ext4
          • Set Kernel Image to <kria project directory>/kv260_custom_pkg/kv260_custom_plnx/images/linux/
          • Select Acceleration templates with PL and AIE accelerators -> Vector Addition 
          • Click Finish
        • In Explorer window, double click on vadd.prj to open new application project
          • Set active build configuration to Hardware
        • In Explorer window, select vadd_system
          • Click on build Icon
        • Prepare for Hardware transfer
          • Convert bit file to bin
        • cd vadd_system/Package
        • echo 'all:{system.bit}'>bootgen.bif
        • bootgen -w -arch zynqmp -process_bitstream bin -image bootgen.bif
        • mv system.bit.bin vadd.bit.bin
        • Open step2_petalinux/dt_output/pl.dtsi
        • Update the line of firmware-name =, type in vadd.bit.bin as its value so that xmutil can load the bitstream. firmware-name = "vadd.bit.bin";
        • Compile pl.dtsi to dtbo with command dtc -@ -O dtb -o step4_validate/vadd.dtbo step2_petalinux/dt_output/pl.dtsi
        • Edit shell.json
          • {
          •   "shell_type" : "XRT_FLAT",
          •   "num_slots": "1"
          • }
        • scp vadd.dtbo vadd.bit.bin shell.json vadd binary_container_1.xclbin petalinux@<SOM Starter Kit IP>:/home/petalinux
        • OnTarget KV260:
          • sudo mkdir /lib/firmware/xilinx/vadd
          • cd /home/petalinux
          • mv vadd.dtbo vadd.bit.bin shell.json /lib/firmware/xilinx/vadd
          • sudo xmutil listapps
          • sudo xmutil unloadapp
          • sudo xmutil loadapp vadd
          • chmod +x ./vadd
          • ./vadd binary_container_1.xclbin

        The final result showed Test Passed.  This proved the flow to create and run an application.  

        The Smart Camera application has a repo that I can modify to allow a RTSP stream input.  This change requires changing the dynamic gstreamer pipeline generation to provide an rtsp_src in main.cpp.  As you can see this is not a difficult change, but without a known working process that a modified application will run, I am not comfortable making any changes.  So my plan is to build a Vitis project for the kv260_ispMipiRx_vcu_DP Hardware platform.  Then import the Smart Camera application project and build.  Unfortunately I was not able to complete this before the end of my evaluation period.  I am glad that I have a path forward that I am confident that I will see success.

        Conclusion

        I am generally happy with the hardware platform of this development kit.  The ability to run a full Artificial intelligence application in a few hours was impressive.  The flexibility to modify the hardware in significant ways is compelling for the advanced user.  Xilinx is targeting this product for software developers with little to no experience to FPGA’s.  I have found that significant development can be done without this knowledge; at the same time they do offer the ability to utilize the FPGA if you choose.  This is impressive since the FPGA offers so much variation in the hardware platform.  

        Xilinx offers a significant amount of tools to develop very complex artificial intelligence applications.  The Vitis AI library allows development with custom integrations for many of the AI open source libraries.  The Vitis Video Analytics SDK helps to use the Gstreamer pipelines on the target.  The Vivado High Level Synthesis tool helps to push more of the design in the FPGA fabric.  This allows the extensible platform to create custom hardware blocks without coding in an HDL language.  The vadd example application used this feature.  The more general FPGA tools are some of the best in the industry.  The FPGA IP blocks that are available allow development without having to create low level blocks.  The ability to configure the IP to best match your platform also helps to control the amount of power needed to run; for example you specify the number of video streams in and out of the VCU video codec before the hardware platform is synthesized.  This means only the hardware that is needed is included in your design.

        My initial experience on this hardware had a Getting Started Guide that did not include everything I needed to know to get up and running.  This had a significant impact on the time to run the first app on the hardware.  This document is the first impression for a new user, and I think it should be the one and only source of information to get up and running.  The document did provide links to other documents, but this required searching the new document for the needed information.  I did get everything up and running but it took significantly longer to accomplish.

        The product I am trying to make with this hardware is an AI appliance that takes data from my network camera and streams it to my Doorbell system.  Since this looked very similar to the Smart Camera Application, I started with the tutorials associated with that application.  I found these tutorials to be insufficient to get a full understanding of the process needed to build an application on a custom platform.  First the example applications did not use the example store that is part of Vivado and Vitis; instead a make flow called a TCL script to create a project and implement the IP.  This did not help the user see the processes they will need to know to do this themselves.  The Vivado project was complete and easily understood, but I have experience with this tool.  The Vitis project was NOT clear after running the make flow to create it.  When I tried to use the Vitis project it felt like I was missing important parts of my platform (BOOT, ROOT_FS, SD-CARD).  

        I was able to get an understanding of the application development process with a tutorial for creating a custom hardware platform and a Vitis application on top of it.  This forced me to load Petalinux, Xilinx’s custom version of Linux.  Through this tutorial I was able to find a path that I know will produce my application.  That being said, I have not actually completed the development of my application.  It took significantly longer to find important information due to holes in the example design tutorials.  All of the needed information was available, but having to search for it took way too long.  

        I do think much of the issues I had with the tutorials and documentation were due to a new focus on using Ubuntu when the official version of Ubuntu was released.  I do like the idea of running a familiar Linux distribution, but not at the cost of having to develop apps that only run in docker containers that have to be built on the target.  Petalinux is a mature distribution that has built in support for the features of this device.  By having full control of the Linux build, it is easy to insert your app on an extremely dynamic hardware platform.  It would be nice to see two flavors of the example designs, one for Ubuntu and one for Petalinux.  

        A lesson learned from this review was that my home equipment was not up to the full task.  The demands on the hardware to run the development tools were significant.  You needed +300GB of hard disk space and more than 16 GB of memory on a computer running the “right” version of Ubuntu.  I was able to get the tools to run, but I had to override the defaults for the number of Jobs.  This was not straightforward in the Vitis tool.  

        My plan for this review was to compare the Kria KV260 to the Jetson Nano.  Since the Nano did not have good performance with video streaming in and out, I thought it would be good to highlight the capabilities of this device.  Unfortunately I did not get that feature working on the Kria yet.  I will say the Nano example designs were complete and the author, Rusty, was very visible to ask directly or through the forums.  

        Note: Some images came from Xilinx Documentation and were used to promote a Xilinx product.

        Anonymous