RoadTest: Avnet Ultra96 Dev Board
Evaluation Type: Development Boards & Tools
Did you receive all parts the manufacturer stated would be included in the package?: True
What other parts do you consider comparable to this product?: I don't know of any other product with the same features and components.
What were the biggest problems encountered?: (1) faulty parts, (2) tutorials were not based on the shipping version of the product and contained instructions which did not correspond to the test device and (3) community-based support lacks accountability and is not adequate for development efforts with a deadline.
This is not a thorough test, but first impressions and the results of a simple “Hello World” test. The Ultra96 has rich capabilities and an exceptional range of processing and interfacing options. Testing of all the board offers will take a bit more time.
What is an Ultra96
The Ultra96 is a Xilinx Zynq UltraScale+™ MPSoC development board based on the Linaro 96Boards specification according to the Ultra96.org description. I’d like to emphasize “development board”. This board is a developer’s dream, combining
In a 85mm x 54mm form factor, based on the Linaro 96Boards Consumer Edition specification (https://www.96boards.org/products/ce/ ).The Zync Ultrascale+ MPSOC is the core of the Ultra96, combining
For the exhaustive list, see the Zynq UltraScale+ Device Technical Reference Manual ( https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf )What is it intended to do?The Ultra96 is designed to be a development board and excels in that role. Other potential applications include Machine Learning, IOT, Video and image capture/processing, and DSP signal applications. Any requirements for
would be good candidates for this board.
Testing it yourself
The Ultra96 Board ships with a Linux distribution on a microSD card which provides a web server accessible via wifi. The home page will show you a number of sample applications including a blinky LED test. The web pages will show source code and allow adding your own tests. It’s a quick and informative introduction to the board.
What do I think?
I like the Ultra96 Board
The Zynq Ultrascale+ MPSoC offers a quad-core RISC processor for applications with a dual-core real-time and GPU devices along with programmable logic. Numerous control and protection features set it apart as a superior application development and prototyping platform. It embodies Xilinx’s strategy of using programmable logic for hardware (PL)-based application acceleration.
Hardware-based application acceleration is the key differentiator for the Zynq Ultrascale+ MPSoC. That is what this device does best and is the reason to use it. It’s no wonder that Xilinx focuses on AI, image processing, IOT, and signal processing as showcase applications.
This is a high-end development board with exceptional processing, communication and management capabilities. At US$249, it’s a great value and an excellent development tool.
Some concerns worth considering
All this comes at a cost. Those stepping up to this board from an FPGA will find that their Verilog/VHDL skills will need to be augmented with C/C++/Python and Linux. All users should be prepared for a moderate to substantial learning curve due to the differences in design as well as sheer abundance of features.
The Ultra96 Board should not be your first experience with an FPGA. For those who need an FPGA without application processing capabilities, this is “Too much sugar for a nickel” (I.e. ” … a lot of trouble for very little return, too much of a bother to fool with”) according to phrases.uk.org ).
Consider the number of steps needed for a simple “Hello World” application described below. To accomplish “blinky lights” tests with an FPGA, a lot fewer steps are needed. The Ultra96 Board is not an FPGA, it is hardware-based application acceleration.
The Xilinx tool set (versions 2018.x) includes support and the usual set of hardware-specific assistance, but if you have been putting off learning the SDK then this board will be the reason you have to dive in. Grab your favorite beverage, put on some patience and get started. There’s plenty of help and you will enjoy the results.
Simple “Hello World” test
These instructions require that Xilinx Vivado 2018.x, both Vivado and the SDK, are installed. The screen shots are taken using Vivado 2018.3. There is an entitlement document in the Ultra96 box that provides instructions on acquiring a license. Instructions for installing Vivado are available on the Xilinx web site.
This test comes nearly verbatim from two Avnet documents,
Ultra96: Creating a Zynq Ultrascale+ MPSOC Hardware Platform in Vivado ( https://www.element14.com/community/docs/DOC-91053/l/01ultra96vivadointro2018201zip )
Ultra96: Hello World
Preparing to test
The first task is to obtain the Board Definition File set from the Avnet Github Folder. Instructions can be found here: http://zedboard.org/sites/default/files/documentations/Installing-Board-Definition-Files_v1_0.pdf .
The Avnet Github Folder is located here: https://github.com/Avnet/bdf
Click the Clone or Download Button.
When the download completes, the bdf-master.zip file will be located in the location you use for downloads.
Locate the directory where Vivado is installed and then find the location for the Board Definition Files in the <<install location>>/<<vivado/vivado_version>>/data/boards/board_files directory. This will be the location for installing the Board Definition Files.
Copy all the directories from the bdf-master directory of the bdf-master.zip file to the board_files directory.
Before running a test on the Ultra96, check to make sure the Board Definition Files are available. Start Vivado and create a new project.
The Vivado New Project Wizard Screen appears. Click on Next.
The Vivado Project Name Screen is displayed, prompting for a project name, and confirming the project directory. The name on the screen shot below is “Validate_BDF”, but can be any name. The project directory name will be the Vivado default project directory. Some Vivado users have reported a limit of 200 characters in the project directory name. The “Create project directory” checkbox is selected. Click on Next.
Select “RTL Project” and “Do not specify sources at this time” from the Vivado Project Type Screen which appears. Click on Next.
Select “Boards” on the Vivado Default Part Screen which appears. A momentary delay may occur while Vivado populates the list of boards.
Type “ultra96” in the Search box. If the Ultra96 Board Definition File has been installed correctly, an entry for “Ultra96v1 Evaluation Platform” will appear. Check that the File Version is “1.2” and the Board Rev is “Rev 1”.
If the entry described above is displayed, the Ultra96 Board Definition Files are available and the “Hello World” test can begin. Decide if you wish to keep the ”Validate_BDF” project name for this test and click on Next, or create a new project and click on Cancel. Creating a new project is recommended.
The Hello World test
To test the Ultra96 Board, a simple “Hello World” test is used. The test process begins by building a generic hardware support platform for the Xilinx Zinq Ultrascale+ MPSoC. Note that the first steps below mirror the steps used to test the Board Definition Files above.
Start Vivado and create a new project.
Click on Create Project. The Vivado New Project Wizard Screen appears.
Click on Next. The Vivado Project Name Screen is displayed, prompting for a project name, and confirming the project directory. The name on the screen shot below is “Ultra96_Basic_System” but can be any name. The project directory name will be the Vivado default project directory. Be sure that the project directory name contains no spaces.
Click on Next. The Project Type Screen appears. Select the Radio Button for RTL Project and click in the Checkbox “Do not specify sources at this time”.
Click on Next. The Default Part Screen is displayed. Select “Boards”. A momentary delay may occur while Vivado populates the list of boards.
Type “ultra96” in the Search box.
The entry for “Ultra96v1 Evaluation Platform” will appear. Check that the File Version is “1.2” and the Board Rev is “Rev 1”.
Click Next. The New Project Summary screen appears.
Click Finish. The Vivado main screen appears.
Click on Create Block Design. The Block Design Options screen is displayed.
Click OK. An empty block design is shown on the right side of the Vivado main screen.
Click on either of the plus signs. The IP Selection List appears.
Begin typing “zynq ultrascale+ mpsoc”” and watch for the selection list to include this item.
Double click on the “Zynq Ultrascale+ MPSoC”. The selection list is dismissed and the Block Design window now shows the Zynq Ultrascale+.
Click on Run Block Automation. The Block Automation Options screen is displayed.
Select both checkboxes on the left side of the screen and also the “apply Board Preset” checkbox. Click on OK. The Options Screen is dismissed, and block automation begins.
When block automation is complete, the Block Design screen is available. Click on the Maximize icon to view the Block Design screen in more detail.
Additional required pins have been added to the design. Connect the clock pins on the Zynq Ultrascale+ by positioning the mouse pointer to the right of the “plk_clk0” connection. The mouse cursor will change shape to a pencil, and green checks will appear on other clock pins.
Click and drag the mouse from “plk_clk0” to “maxihpm0_fpd_aclk”. A connection line will be displayed indicating that a connection has been made. Repeat this, connecting “plk_clk0” to “maxihpm1_fpd_aclk.
Once the connections are complete, the Block Design screen should look something like this:
Click on the Validate Design (checkbox) Icon. Once validation is completed, a success message will appear. Click on OK in this message box.
Click on the Save Block Design icon to save this design.
Click on the Restore icon to show the portions of the Vivado main screen that were obscured when the Block Design screen was Maximized.
Click on Regenerate Layout to reposition the design elements for better visibility.
Click the Sources Tab to show the design sources.
Right click on the “design 1(design_1.bd)” entry under Design Sources.
In the context menu that appears, click on Create HDL Wrapper.
The Wrapper Option screen is displayed. Make sure that “Let Vivado manage wrapper and auto-update” is selected.
Click OK. Notice that the Design Sources tree has a new “design_1_wrapper” entry.
Click on Generate Bitstream. The Generate Bitstream Options Screen is displayed.
Set the number of processing cores. Remember to count hyperthreaded cores. This item sets the limit on the number of concurrent generation tasks that Vivado will run, so it’s important to not exceed the actual number of processing cores available. In most circumstances, Vivado will suggest and appropriate count.
Click OK. Vivado begins to create and run generation tasks
Once the generation tasks are spawned, the status of all tasks is shown on the Vivado Main Screen.
The Bitstream Generation Completed screen appears once all tasks have completed.
Make sure that “Open Implemented Design” is selected. Click OK. The Vivado Main Screen now shows a Device Map (no, it’s not a video game from the 1980s).
Click on File, then Export, then Export Hardware. The Export Hardware Options screen is displayed.
Click on “Include Bitstream” then click OK. The Vivado main screen remains displayed.
The contents of the project directory are shown here:
The directory with an “sdk” extension contains the exported hardware definition which will be used by the Xilinx SDK in the following steps.
The file with the “xpr” extension is the Vivado project file.
The directories with cache, hw, runs, sim and srcs extensions contain design sources, wrapper HDL and results of synthesis and implementation. These are the files supporting the hardware design.
Returning to Vivado, continue with the test by clicking File, then Launch SDK.
The Launch SDK screen appears. Click OK. The SDK Options Screen is displayed.
There will likely be a noticeable interval while the SDK launches. A welcome screen and an importing progress bar will appear and be removed automatically. There is no need to do anything until the SDK Main Screen appears.
The files shown in the Project Explorer Panel are in the Hardware Platform directory, located in the design_1_wrapper_hw_platform_0 directory of the Ultra96_Basic_System.sdk directory in the Vivado Project Directory shown above.
Returning to the SDK, click File then New then Board Support Package.
The Board Support Package Options screen appears.
Click Finish. The Board Support Package Settings screen is displayed.
Click standalone, then click on the drop-down under Value for stdin and select psu_uart_1. Repeat the selection for stdout. Click OK
The Board Support Package is created and added to the project. Expand the “standalone_bsp_0” and then the “psu_cortexa53_0 items in the Project Explorer panel to see the contents of the Package.
Click on File then New then Application Project.
The Application Project Options screen appears.
Enter the Project name, “Hello_Ultra96”, then select the “Use existing” Radio Button and select the Board Support Package from the Project Explorer Panel. Click Next.
The Application Template Screen is displayed. Select “Hello World” and click Finish. The application is generated. Expand the “Hello_Ultra96” item in the Project Explorer to see the contents.
It’s time to connect hardware. The Ultra96 Board must be connected to the workstation where Vivado and the Xilinx SDK are running in order to load the program just created.
Note that the components are pictured on a static-resistant mat. They were handled with a wrist-attached static strap and any contact with switches or buttons was made with a non-conductive tool (a non-metalic spudger in this case).
I mention these things to emphasize the importance of reducing the risk of ESD. Here in the Washington, DC area, it's winter and the home heater runs frequently, increasing the chances of static discharge. A little caution is better than shipping delay (and the risk of stock shortages) for the replacement of damaged parts).
Here are the needed components:
The Ultra96 Board
The JTAG POD (adapter)
The Power Adapter
A cable with a micro USB connector is also required.
To connect the JTAG POD, look at the side of the POD with two connectors. One is a 3 pin UART connector (J2). The other is a 7 pin JTAG connector (J3). The single page guide included in the box with the POD mis-labels the connectors.
The JTAG POD is extremely sensitive to ESD, according to discussion boards. Wear a grounding strap and use a static mat as advised above. Note that the two connectors on both the POD and the Ultra96 Board are on different sides of the PCB, so careful handling is required.
Insert the JTAG POD UART Connector into the J6 Connector on the Ultra96 while inserting the JTAG POD JTAG Connector into the J2 Connector on the Ultra96.
The quality of this photo does not match that of other photos in this test.
Connect the power and USB connectors.
Set the Boot Mode Switch (SW2) to JTAG (both pins set too on, or toward the outside of the PCB).
Connect the power cable. No LEDs on the Ultra96 Board will illuminate.
Connect the USB cable to the workstation used to run Vivado and the Xilinx SDK. The RDY LED on the JTAG POD will illuminate.
Determine the port number assigned to the USB cable using an OS-specific tool.
Press and release the Ultra96 power button (SW3). The power on (DS9) and the four user (DS2-5) LEDs on the Ultra96 Board will illuminate.
Return to the Xilinx SDK and select the SDK Terminal Tab near the bottom of the screen. Click on the green plus sign to the right.
The SDK Serial Port Parameters screen will appear.
Enter the port number determined above, then set the Baud Rate to 115200. Verify that Data bits is 8, Stop bits is 1, Parity is None and Flow control is None. Timeout is optional.
Click OK. A connection confirmation message is displayed in the terminal window.
Load the Hello_Ultra96 and supporting programs on the Ultra96 Board by clicking on the red and green Program FPGA Icon.
The Program FPGA Options screen is displayed.
Click Program. When this is complete, the message “FPGA configured successfully…” will appear in the SDK Log Window to the right of the terminal window.
To execute the program, right-click on the program name (Hello_Ultra96) in the Project Explorer, then click on Run As, then click on “1Launch on Hardware (System Debugger)”.
Watch the messages in the SDK Log window for any errors. When the message activity ceases, select the SDK Terminal Tab.
The “Hello World” message indicates a successful test.
This is a capable, even exceptional, high-end hardware-based application acceleration device. It’s an obvious choice for this purpose. Xilinx and Avnet have clearly thought through what it takes to make the top contender in this application space.
The board’s use of the 96Boards specification makes integration much easier. An active community and wide range of 3rd party enhancements will help you develop and deploy complex applications quickly.
Nice roadtest review. Too bad that your JTAG pod was damaged/inoperable. That sure would make it difficult to fully utilize this tool (good thing that you were able to borrow a pod). I look forward to…
Nice walk through of the menus to get started.
Thanks a lot for writing up the review!
Thanks a lot for writing up the review!
Nice walk through of the menus to get started.
Nice roadtest review. Too bad that your JTAG pod was damaged/inoperable. That sure would make it difficult to fully utilize this tool (good thing that you were able to borrow a pod). I look forward to see more information as you move beyond the "hello world" test.