Hercules microcontrollers, DMA and Memory Cache

2 Jan 2016

DMA and memory cache don't always play nicely together.

I had an issue when trying to use serial communication and DMA on a TI Hercules controller. The DMA data wasn't appearing in my read buffers.

TI's application specialists helped me to resolve my issues. It was related to ARM memory cache settings.

I've written a step-by-step guide on the hackster.io forum on that subject.

Due to the subject, this hasn't turned into an easy-to-read novel. I hope it may help fellow developers struggling with similar issues.

When you're playing with DMA, you think everything is working ok, and you don't see any data written to your variables, this post may be worth looking into.
It's based on an SCI example, but applicable in many DMA situations.

Default Cache configuaration is write-back:

For DMA relevant buffers, you can specify a chunk of RAM with write-through configuation.

There's more to do than just setting aside a portion of the memory. Check the video for a quick overview, and the hackster.io blog post for a step-by-step explanation with a working project attached.

The Series
0 - Buffers and Parallel Data Lines
1a - Buffers and DMA
1b - SPI without Buffers
2 - SPI with Buffers
3a - SPI with DMA
3b - SPI with DMA works
4a - SPI Master with DMA and Parallel Data Lines
Hercules microcontrollers, DMA and Memory Cache

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DAB over 9 years ago

Great post Jan.

DMA can be very useful, but I want to make sure that everyone understands that DMA works by stealing CPU cycles.
Each DMA action will slow down your normal algorithm processing. Usually by a small amount, but if you use a lot of DMA, it can add up to be a significant affect on your timing budgets.

DAB
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Jan Cumps over 9 years ago in reply to DAB

It seems that in the Hercules family, the memory DMA transfer doesn't use any CPU cycles:

Application Report: SCI With DMA

Page 5:
Without the DMA the CPU would have to move data to the SCI after every buffer sized bytes. With the DMA the CPU is free for the entire message transmission.

I couldn't find a firm source outside of that document
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DAB over 9 years ago in reply to Jan Cumps

It would take an interesting hardware design to make it happen without affecting overall CPU performance.
The easiest way would be to copy the data into a separate memory buffer, but the copying would still use CPU cycles.

If you find out if they indeed can do DMA without CPU cycle stealing, let me know. They should have a very interesting architecture solution to make it happen.

DAB
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Jan Cumps over 9 years ago in reply to DAB

I like to think that there's a minion inside shoveling the data back and forth
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clem57 over 9 years ago in reply to Jan Cumps

i found him!
Clem
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clem57 over 9 years ago in reply to Jan Cumps

i found him!
Clem
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