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Embedded and Microcontrollers
Embedded Forum CPLD P-Mosfet Output Circuit - Will it Work?
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Forum Thread Details
  • State Suggested Answer
  • Replies 17 replies
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  • mosfet
  • cpld
  • altera
  • max_v_cpld
Related

CPLD P-Mosfet Output Circuit - Will it Work?

oldmanraskers
oldmanraskers over 10 years ago

Could someone please offer their opinion on whether my circuit would work well for turning on an output via a CPLD. The output voltage at PIN0 will be 3.3V. I want logic 1 to turn on my Q1.

Regards, oldmanraskers.

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  • jw0752
    jw0752 over 10 years ago +2
    Hi, I set up your circuit on LTSPICE and there are a couple problems. First of all I am assuming that you are putting a load between Vdd and the drain of your MOSFET. Second your choice of IRF9530 will…
  • jw0752
    jw0752 over 10 years ago in reply to oldmanraskers +2 suggested
    Hi oldmanraskers, Here is the SPICE file for the simulation that I ran. If you don't have the LTSpcie program yet just go to the Linear Technologies web site and down load it as it is free. It seems that…
  • jw0752
    jw0752 over 10 years ago +1
    Hi , A little follow-up. Here is a web site that explains how to bias the P Ch MOSFET IRF9530 in case you need to use it. http://www.electronics-tutorials.ws/transistor/tran_6.html Here is an excerpt on…
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  • michaelkellett
    0 michaelkellett over 10 years ago

    In addition to the comments from others I'll add these:

     

    1)      When the CPLD powers up or is reset  the output pin will have a default state - you must decide if you want the power switch to be on or off at this point and design the biasing accordingly.

     

    2)     I'm not sure why you are using an opto isolator to drive the MOSFET - is this really necessary, what is the load you are switching  ?

     

    3)     Is additional protection of the switching device required, like inductive spike suppression or current limiting ?

     

    MK

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  • michaelkellett
    0 michaelkellett over 10 years ago

    In addition to the comments from others I'll add these:

     

    1)      When the CPLD powers up or is reset  the output pin will have a default state - you must decide if you want the power switch to be on or off at this point and design the biasing accordingly.

     

    2)     I'm not sure why you are using an opto isolator to drive the MOSFET - is this really necessary, what is the load you are switching  ?

     

    3)     Is additional protection of the switching device required, like inductive spike suppression or current limiting ?

     

    MK

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  • oldmanraskers
    0 oldmanraskers over 10 years ago in reply to michaelkellett

    I'm using the opto because I'm experimenting with stuff, I guess I could use a standard NPN transistor - I am using the circuit to drive small solenoids that will eventually form a lock - they draw about 240mA. It appears to me now, that I have my FET in upside down, and in regards to spike suppression I will need some kind of flywheel diode I think.

    Regards, oldmanraskers.

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  • johnbeetem
    0 johnbeetem over 10 years ago in reply to oldmanraskers

    oldmanraskers wrote:

     

    I'm using the opto because I'm experimenting with stuff, I guess I could use a standard NPN transistor - I am using the circuit to drive small solenoids that will eventually form a lock - they draw about 240mA. It appears to me now, that I have my FET in upside down, and in regards to spike suppression I will need some kind of flywheel diode I think.

    Regards, oldmanraskers.

    For driving that kind of load, I would suggest using NPN Darlington pairs, such as the TI ULN2003A or similar.  Those can sink a lot of current and have built-in flyback diodes.

     

    To get a lot of current through a FET, you need a gate voltage that's higher (or lower for PFET) than your normal logic voltages.  For example, you get a small IC called a "high side switch" that uses a charge pump to boost the an NFET's gate voltage.

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