CPLD P-Mosfet Output Circuit - Will it Work?

A good plan to have  a simulation running the design. Barring that check out MOSFET as a Switch - Using Power MOSFET Switching to determine the various outputs on the P-Mosfet.

clem

Hi,

I set up your circuit on LTSPICE and there are a couple problems. First of all I am assuming that you are putting a load between Vdd and the drain of your MOSFET. Second your choice of IRF9530 will not work. IRF9530 is a P channel Enhanced MOSFET. An N Channel MOSFET like IRF511 will work in your application if the load is between Vdd and the drain of the  MOSFET.

Here is a schematic:

If you can run LTSPICE I can send the simulation to you too. Let me know if you hve further questions.

John

Hi ,

A little follow-up. Here is a web site that explains how to bias the P Ch MOSFET IRF9530 in case you need to use it.

http://www.electronics-tutorials.ws/transistor/tran_6.html

Here is an excerpt on the P channel specifically. Incidentally this is a great site for basic information.

From Electronic Tutorials. See Link above

John

Hi Clem,

Sorry I didn't notice that you had already recommended the Electronic Tutorial website when I posted my follow-up.

John

In addition to the comments from others I'll add these:

1)      When the CPLD powers up or is reset  the output pin will have a default state - you must decide if you want the power switch to be on or off at this point and design the biasing accordingly.

2)     I'm not sure why you are using an opto isolator to drive the MOSFET - is this really necessary, what is the load you are switching  ?

3)     Is additional protection of the switching device required, like inductive spike suppression or current limiting ?

MK

Hi John,

Thanks for the reply - I've never used LTSpice so yeah I'd be interested to see the file. Thanks.

I'm using the opto because I'm experimenting with stuff, I guess I could use a standard NPN transistor - I am using the circuit to drive small solenoids that will eventually form a lock - they draw about 240mA. It appears to me now, that I have my FET in upside down, and in regards to spike suppression I will need some kind of flywheel diode I think.

Regards, oldmanraskers.

Hi oldmanraskers,

Here is the SPICE file for the simulation that I ran. If you don't have the LTSpcie program yet just go to the Linear Technologies web site and down load it as it is free. It seems that I do not know how to give you an executable file in this posting. Here is the bitmap of the circuit that I put into LTSPICE. You can download the program and draw the schematic and run it. Signal Supply V1 is 3.3Volts square wave with 2 uSecond rise and fall time. 10 millisecond Duration and 20 millisecond Period.  Power supply V2 is just 12 Volt DC.

John

oldmanraskers wrote:

 

I'm using the opto because I'm experimenting with stuff, I guess I could use a standard NPN transistor - I am using the circuit to drive small solenoids that will eventually form a lock - they draw about 240mA. It appears to me now, that I have my FET in upside down, and in regards to spike suppression I will need some kind of flywheel diode I think.

Regards, oldmanraskers.

For driving that kind of load, I would suggest using NPN Darlington pairs, such as the TI ULN2003A or similar.  Those can sink a lot of current and have built-in flyback diodes.

To get a lot of current through a FET, you need a gate voltage that's higher (or lower for PFET) than your normal logic voltages.  For example, you get a small IC called a "high side switch" that uses a charge pump to boost the an NFET's gate voltage.

I have looked at my circuit again and come up with this one. The FET is not the exact one that I'm going to use but I think it would do the job regardless. I considered replacing R4 with a Zener but I'm not sure that is really warranted - what do you think? I'm still sticking with MOSFETs just because I obviously don't know enough about them and want to investigate them further. I do have a question regarding R3 though - I have noticed that the larger R3 is made the slower the gate takes to reach the correct voltage - I assume this is capacitance related to the gate, but I don't understand how to decide what values of R3 would cause me problems - any pointers?

Let me know what you think and thanks for your input thus far.

Regards, oldmanraskers.