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DCM in FPGA

Former Member

Hi All,

i need  to divide my CLK form 100Mhz to 200Hz. Can i do it with DCM?

what is minimum freq till DCM works optimium.

 

Thanks to All

Noman

  • Why should you need a DCM to divide your clock by 500,000 - you can do this in the fabric easily.

     

    If you want to understand the DCM then I suggest you start by reading the manual - (ug382.pdf on Xilinx's website (you should read the data sheets for the chip you are using as well)).

     

    If there are things in the guide or data sheet that you don't understand then come back and ask about them. Expect to spend at least a day getting enough of  a feel of the DCM to think about using it.

     

    MK

  • I agree with: just use the fabric.  With 100 MHz, you probably want to do the division in two stages.  Dividing 100 MHz to 200 Hz is a lot to squeeze into a 10 ns cycle, so I suggest having a prescaler followed by the regular counter, as I do in Experiment 2 of this 'blog: First Experiments with the ValentF(x) LOGI-Pi.

     

    You can also use a DCM as a prescaler, which lets you distribute a lower-frequency clock which may save power.  OTOH, the DCM may end up using more power.

     

    I sometimes use an advanced trick where I use a gated clock as a low-speed clock to save power.  I do this in my Flavia project.  if you're interested, see module FlaviaClk in FlaviaX6.v in Data files for FlaviaLP60 release 0.0q for LOGI-Pi.