Latch ciruit Design Problem/Sugguestions

Hi! I'm working on a project which needs latch circuit in my design, which use for Power on/off by hardware and software...

VBAT is 12V. so I put it through a LDR to logic 3V3.

First I have a latch switch, when logic 3V3(pin2) connect to pin1. The top Pmons ON then power up the device.

When the logic 3V3(pin2) connect to pin3, off_requ gose high(1) then go in some MCU input. The MCU will do some proccess., then set output off_pwr to hight (1) to disable the top Pmos.

Will the below diagram works as I discribe above ? Feel free to give me some suggestion for improve design !

thank you so much if you do so!

Latch circuit

Top Replies

dougw over 3 years ago +1

This should work fine. You can reduce the power in the on state by using N channel FETs instead of bipolar transistors. Something like BSS138. or 2N7000.

dougw over 3 years ago

This should work fine. You can reduce the power in the on state by using N channel FETs instead of bipolar transistors. Something like BSS138. or 2N7000.
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Chuitoto over 3 years ago in reply to dougw

Thank you for your reply!! The BSS138 seems like a good option! Do you think increasing the resistance value would reduce the power too? let's say 100K

And also, Any advice model of the top PMOS? capable of such a high V? since that control a JetsonNANO VBAT is 12V and the currect may pass through <= 0.5A

like ... SI2343DS I randomly search online (SOT23-3)
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dougw over 3 years ago in reply to Chuitoto

Yes, increasing the resistances will help reduce power. SI2343DS looks fine.
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phoenixcomm over 3 years ago

man, you like to spend money. use this instead works great with AC no mus, no fuss.

Just make sure the relay contact can deal with the current, and lastly make sure the relay is rated for continuous operation.
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