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Blog GaN FETs Give DC-DC Converters Big Improvements
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EMI-Reduction-Techniques
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  • Author Author: kkazem
  • Date Created: 5 Dec 2021 10:40 PM Date Created
  • Views 2950 views
  • Likes 13 likes
  • Comments 5 comments
  • gallium_nitride
  • dc_dc_converter
  • Design
  • power
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GaN FETs Give DC-DC Converters Big Improvements

kkazem
kkazem
5 Dec 2021

I've recently designed a 650 Watt DC-DC Buck Converter for a satellite and I chose to use GaN FETs for both the series switch and for the synchronous rectifier. For this power range, I could not believe how small these new generation 5, chip-scale GaN FETs are that are made by EPC Corp. A chip-scale device is basically the individual FET die, cut from the GaN wafer, but not put into a package such as the typical TO-220. Instead, the FET gets passivated, which is a type of covering to protect the top-side of the die. The passivation is for the protection of the GaN structures, with leads that protrude thru the passivation layer. The GaN FET process is similar to the structure of a Silicon IC, or a PC Board and can have many layers with the GaN placed over the Silicon substrate. The chip-scale packaging allows for very low lead inductance and efficient cooling thru the top-side (Silicon substrate side) of the FET. GaN is useful for space applications in that it has a high immunity to un-commanded turn-on by ionizing radiation. This is due to it's wide bandgap compared to Silicon.

The GaN FET I used is the EPC2218, with actual size of just 4.1 x 1.6 mm (0.16" x 0.063") and there were two FETs used, one for the series switch and one for the synchronous rectifier. This FET is rated at 100V, 60A, and has an RDSon of just 3.2 mΩ. I ran these FETs at full 667 watt output power on the bench with no heatsink and no fan and they did get somewhat hot, about 120° C, but these GaN FETS can take about 300° C without damage. However, the solder would melt if it was run that hot. The FETs have an epoxy underfill to avoid them breaking loose from their solder pads and moving if the solder ever melted. The input was 40 VDC and the output was 29 VDC. The measured efficiency was 97.8% which included the loss in the inductor and pcb traces. I chose a modest switching frequency of 500 KHz, but these GaN FETs switch so fast, they can easily be run at 2-3 MHz or higher.

The SMD leads are oval-shaped solder bumps on the FET as can be seen in the first photo of the bottom-side (lead-side) of an EPC2218 FET. The GaN's lead bump side becomes the bottom-side of the FET and gets soldered to the PCB, similar to the way a BGA gets soldered, except that the leads are oval and not spherical.  The top-side of the FET is, therefore, from the bottom-side (substrate) of the GaN wafer.  The substrate, or bottom layer of the GaN FET is Silicon upon which GaN features are deposited in a complex manufacturing process. The Silicon substrate allows the devices to be manufactured using standard Silicon IC photolithographic processes and equipment. The top of the GaN FET is actually from the die's substrate and since it has no features etched into it, it doesn't need any passivation for protection. It's from the bottom of the Silicon wafer upon which the GaN features are deposited and is doped Silicon. Here's a link to the EPC2218 datasheet: https://epc-co.com/epc/Portals/0/epc/documents/datasheets/epc2218_datasheet.pdf 

The last photo is of an EPC90123 Evaluation Board using the EPC2218 GaN FETs.  The FETs can be seen in the red box with the white arrow pointing to one of the two FETs. The entire board is only 50 x 50 mm (2" x 2"). As you can see, these FETs are tiny, especially given the power they're converting. The EPC90123 eval board photo is from the EPC90123 Eval Board user's guide and does not show the CoilCraft inductor I used, which was P/N: AGP4233, 6.8 uH. The DC-DC Converter's full load output current is over 23 amps DC at 29 VDC, for 667 watts output power. The eval board requires the user to supply their own inductor and output cap. I used a 10 uF, 50 V, MLCC cap, a TDK P/N: CKG57NX7R2A106M500JJ. I should also mention that the EPC90123 eval board can be configured as either a Buck or as a Boost converter. Additionally, it has provision for heatsinking.

As much as I would encourage everyone to experiment with GaN FETs, I don't recommend breadboarding your circuit. Due to the high switching frequencies involved, it's critical that a PC Board is laid-out for your design with good high-frequency design and layout technique used. The EPC webpage for their EPC90123 Eval Board is a good place to start.
The link is:  https://epc-co.com/epc/Products/DemoBoards/EPC90123.aspx and this page has links to the Schematic, Gerber files, the Quick Start Guide, a Bill of Material, and more. 

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  • torg
    torg 7 months ago in reply to kkazem

    Hi again kkazem,

    Thank you for the explanation and detailed answer (and for following up on a 3-year old post) much appreciated. For board layout and good practices I also found the following guide from EPS really informative.

    youtu.be/hYglBjqw6j0

    I was interested in what kind of setup you used for driving the GaN FETs in the buck converter satellite application. Did you design the drive circuitry yourself or did you use some of the ICs available like the LM5140-Q1 or the LTC7890? 

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  • kkazem
    kkazem 7 months ago in reply to torg

    Not sure what you mean exactly by "set up the drive circuitry", but I'll elaborate a bit.

    With GaN, the gate drive voltages, Vgson and Vgsoff, you have to be careful to not puncture the gate oxide by an overvoltage. The EPS GaN fets are optimized for 5V Vgson. The drive circuitry must be designed to prevent any ovrrvoltages beyond about 5.5v including inductive spikes.

    Many engineers don't appreciate how fast these fets switch and how high the peak drive current is. Even with moderate trace lengths, special steps must be taken to limit the peak gate drive voltage spikes to 1/2 volt. That relatively small spike brings the Vdson up to the safe limit of 5.5v when using a 5vdc supply on the gate drv ckt. 

    Things like zener diode clamps, short traces between the gate drv ic and the fet gate and source terminals are critical to prevent damage to the fet. 

    For best results, a gate drv Ic with min 3 to 6 amps peak is needed. A min 4 layer pcb is an absolute must and it must have a gnd plane layer opposite the side the gate drvr ic is placed.

    Also, turn on/off times should be less than 10nS with a separate series gate resistor on each fet in parallel if using multiple fets per switch location.

    Bottom line is that using GaN fets is much more involved than the slower Si fets. A SPICE model should be run in LTSPICE or similar ckt simulator on the gate drive ckt with the model including most parasitic components. Much more care and detail in the design must be used.

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  • torg
    torg 7 months ago

    Interesting read Kkazem, thanks for sharing.
    I would be interested in knowing how you set up the drive circuitry for the EPC2218. 

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  • kkazem
    kkazem over 3 years ago in reply to navadeepganeshu

    Thanks. I'll check that out.

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  • navadeepganeshu
    navadeepganeshu over 3 years ago

    Interesting!

    Just came across Dr. Ray's series of posts on GaN on linkedin and here is a video https://youtu.be/pmGu_Hjwp3o

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