Issues With MOSFET bridge, DC motor 24V 200W

R1 may be too high of a value. It will take time to charge the gate capacitance, which will turn the FET on slowly, causing heat losses.

If R1 is made smaller, it may discharge the capacitor too fast to keep the FET on.

You may need to drive the gate with a push pull transistor pair so it turns on and off quickly without discharging the capacitor.

You also need to ensure that Q1 and Q2 are never turned on at the same time. If Q1 is slow to turn off, Q2 will pull current through it, heating it up.

The same problem happens to Q2 if it is slow to turn off.

You need a delay between turning each FET off and turning its counterpart on.

When you say to drive the gate with a push pull pair, are you referring to both High side and Low side FETs.

For experiment, I gave IN_1 a permanent zero volt and IN_2 a permanent 5V. Turning on Q1 and Q4. Do I still need to consider the rise time since the gate is always ON?

Also, the Ciss is around 1.5nF that will give me a rise time of 15us roughly with the 10K resistor. If I use a PWM of 10KHz, then also this rise time may work ?

Is the capacitor discharging when T1 is on to the point where there is no boost to the gate - which would mean Q1 is only partly turned on?

By push-pull I mean put a stage like this on the output of T1, this would allow a large value for R1 that would not discharge the capacitor so fast:

Maybe take a look with a scope to see if you are getting shoot thru, i.e. forward and reverse bridges firing at the same time or with some overlap.

Do bridges have solid interlocking and deadband ?

Are you running no load, or with load ?  Try running motor uncoupled to see if heating changes significantly.

Got that, this will help me reduce the charging slope during the positive and negative triggers. Tried this circuit too for feeding to the gate, still the upper MOSFET is heating.

Some more observations :-

At Supply voltage 27V, when T1 base is pulled down and T2 pulled up.

Gate voltage at Q1 is 25V, Drain source voltage at Q1 is 2.5 volts and Drain source voltage at Q4 is zero.

This suggests that Q1 is not turning on properly.

Is the bootstrap not working correctly? Am I missing something?

Thanks

On no load it is working fine. As I apply some load to it, the upper MOSFET starts heating. And I checked there are no shoot thru, apparently the other two MOSFETs stay off during the whole process.

As far as the deadband is concerned, I am giving 100% duty to the Q1 and Q3 MOSFET and zero duty to other to.

I got some measurements though,

At Supply voltage 27V, when T1 base is pulled down and T2 pulled up.

Gate voltage at Q1 is 25V, Drain source voltage at Q1 is 2.5 volts and Drain source voltage at Q4 is zero.

Does this suggests anything?

Thanks

It sounds like you should remove the pull down resistor on the gate of Q1.

Or maybe it should be between the Q1 gate and T1 collector.

Yes I tried to remove the pull down  resistor - same effect.

Will try with multiple iterations of series gate resistance and see if I get any better response.

Thanks

What is the voltage on the boost capacitor? It seems it is not high enough...

It's a bad idea to drive a power mosfet this way. First of all, the Supply Voltage is 24 VDC and the FET's max gate voltage is only 20 V. Therefore, you can expect FET failures via puncturing the gate, though it probably won't happen right away.  Second, as the turn on path is thru a 10K resistor, the maximum gate charge current is only 2.4 mA peak and reduces as the gate charges up. This would translate into a turn on time of about 37 uS, which is much slower than optimal, causing high FET switching losses. It's not as bad for turn off as the T1 NPN can sink 100-300 mA. A proper FET driver should source and sink at least 1.5 amps for a FET this size for fast switching in the 50-200 nSec range. A cascade (totem-pole) NPN-PNP arrangement (or n-CH-p-CH in MOS) using discrete parts can be used, but the drive supply should be limited to 12 to 15 VDC typically. Even if the FET gate is rated at +/-30V, there's no real advantage to driving the gates that high as they're typically fully enhanced at 10-12 V Vgs. One good, low-cost method for gate drive is to use a CMOS hex inverter or buffer and parallel all of them. Note that you cannot use half the inverters to drive the upper FET and half for the lower FET as the H-Bridge FET Sources are at different grounds. Therefore, you would need two inverter or buffer ICs. The 10uF cap used for the bootstrap supply is a bit high. For this size FET, having Qg (total gate charge) of 90 nanoCoulombs max, a 0.1 uF (100 nF) is more appropriately sized. If the switching frequency is relatively low, as it would be for a motor controller, the 10 uF may work fine, but more than 100 nF isn't needed. In many H-Bridge circuits, it's preferable to have the turn-off speed be faster than the turn on. This is usually done by having a separate resistive circuit for the turn-on & turn off using about a two series resistors with a diode across one of them with the cathode pointing toward the driver. For example, a 5 ohm and a 15 ohm resistor with a 1N4148 across the larger resistor. This effectively gives the turn on circuit 20 ohms series and the turn off just 5 ohm series resistance so that the turn off is substantially faster than turn on. This will help to avoid or minimize Cross-Conduction (aka shoot thru current) in the H-Bridge.