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Blog Executing Vivado Design Suite TCL Commands
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  • Author Author: guillengap
  • Date Created: 6 Jun 2023 8:42 PM Date Created
  • Views 1289 views
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  • design challenge
  • xilinx
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Executing Vivado Design Suite TCL Commands

guillengap
guillengap
6 Jun 2023
Executing Vivado Design Suite TCL Commands

Blog # 1 - Project Description And Upgrade Installation
Blog # 2 - MiniZed Board Peripheral Configuration and Creating a Boot Image
Blog # 3 - Executing Vivado Design Suite TCL Commands
Blog # 4 - Move Data Between BRAM and DDR3 Memories
Blog # 5 - How to Enable Interrupts With MiniZed

**********************************************************************************************************************

In this blog I am going to show you the TCL commands used in the Lesson 4 training course, and on Windows 10. I also indicate you an erratum of the publication, and some TCL commands I experienced in this lesson.  MiniZed Hardware Technical Training 2021.1: Lesson 4 

  • The use of the "pwd" command is to show us the current directory.
  • Tutorial notified us that slashes for the directories are forward slashes, not backslashes as Windows uses. I did both tests as you can see in the image above.

image

the "cd" command is used to change directory.

image

From the TCL console we can open a project as follows: open_project ./ZynqDesign.xpr

image

We open the block design with the following command: open_bd_design ./ZynqDesign/ZynqDesign.srcs/sources_1/bd/Z_system/Z_system.bd

image

A list of interfaces ports, type: get_bd_intf_ports

image

Create an output port for reset type: create_bd_port -dir O -type rst Reset

image

We can ask for help regarding any command as follows: help write_bd_tcl

image

Next, we’ll export the block design using this command: write_bd_tcl basic_design.tcl

image

If we open this file we can see that this block design encompasses all connections and IP in the design, and also the IP configurations.

image

Erratum

Step 13 of lesson 4 says:

image

This command just omits the file name. Below I show the corrected command: write_project_tcl project_setup.tcl -paths_relative_to C:/training/AvnetTTC/ZynqHW/2021_1/ZynqDesign_lab4

image

Other TCL command examples

Below I show you some simple commands that you can find on the official site:  

  • The following example validates the IPs in the current project: validate_ip -save_ip [get_ips]
  • The following example verifies the bitstream on current hardware device: verify_hw_devices [current_hw_device]
  • The following example returns only the version number for the software: version -short
  • The following example writes both the binary and ASCII forms of the bitstream: write_bitstream -raw_bitfile C:/Data/design1
  • The following example exports a CSV file from the current project: write_csv C:/Data/pinList.csv
  • The following example write a debug probe file from the current design: write_debug_probes C:/Data/designProbes.ltx

Reference:

  • https://docs.xilinx.com/r/en-US/ug835-vivado-tcl-commands

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