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Welcome to the final blog on building a Bottle Cap Inspection System using Machine Vision. In this project, we plan to create an automated visual inspection system that can detect defects in bottle caps, such as cracks, deformation, and missing parts…

Welcome to blog 5 for the Ultra96-V2 development board. In this blog, we'll dive into interfacing an LCD Click board with the Ultra96-V2, allowing you to display information, messages, or graphics on an LCD screen. Let's get started! LCD mini click…

In this tutorial, we will guide you through the process of interfacing the LMS6DSL Click Mezzanine with the Ultra96-V2 development board using Xilinx Vitis. The LMS6DSL Click Mezzanine is equipped with a sensor that can measure both acceleration and angular…

In this blog post, we will set up the Vitis IDE, where we will walk through the process of creating a workspace, configuring a Platform project, and creating an Application project. The final stage in the hardware export…

Introduction: The final project is based on AI/Machine Learning within the Core Technology Path. The aim of the project was to accelerate object detection and localisation on ultra96v2. I have some prior experience in FPGA design, but this is my first…

In this blog, we will be working on the process of printing messages to the serial port on the Ultra96-V2 development board. Serial communication is a fundamental method for interacting with embedded systems, allowing you to monitor and debug your FPGA…

Table of Contents Vitis AI Camera support Real-Time Vitis AI It is an interesting project from AMD to run inference development solutions. There are several versions of Vitis AI. This time, compared with the last post with PYNQ Computer…

As a continuos increasing need, holes in driveways must be fixed in order to preserve cars and reduce maintanance of driving population. It is known that holes might cause traffic jams, accidents and even deadly car crashes. It is also an expensive…

Introduction Hi everyone! In this blog I will show you my final project of the "Path to Programmable III" challenge. This idea was inspired from the project published by Adam Taylor : Mini But Mighty, the MiniZed and Vitis for Motor Control . As an…

All my previous blogs have been mostly experimenting with Vivado, Vitis and Petalinux tools for design and implementation as the training material has be based on it. I planned the final Training blogs to try an image processing application on ultra96…

Software Training Lesson 6: Connecting Hardware and Debugging Summary of Lesson6 Ultra96 V2 Hardware Explanation How to Debug the application using RUN configuration Setup for Processor initialization, RESET, Download Bit steam, Terminal…

Introduction I could have done so much more with the Ultra96v2 board, I stuck with the theme of LED blinking through different ways and although it is not too fancy, one thing that I have noticed is that I spend too much time when it comes to creating…

1. Introduction In this last part of the series, we are going to run a simple CNN model in our Ultra96v2 after we quantize and compile it for the board. The CNN is trained on MNIST and the original plan was to identify the test number using the CNN…

1. Introduction In this blog, we will extend our previous LED blinking example to again blink more LEDs. We will see how we can use PYNQ to program our FPGA. In this design, we will use the low speed expansion header in the Ultra96v2 board to connect…

1. Introduction In the last blog, we just used the Processing System (PS) side to blink the 4 user programmable LEDs, so we will build on that and see how we can incorporate the PL side LEDs and extend our design to use both the PS and the PL. In this…

1. Introduction In this blog, we will use the Processing System (PS) side to blink the 4 user programmable LEDs that are available in the Ultra96v2. This is a really simple introduction to how we can initialize the Zynq US+ block in the Vivado design…

This is my Fourth training blog as part of the Path to Programmable 3 design challenge. As mentioned in the First Blog , this blog will be focussed on Vitis. I will give an overview about Vitis, its features. Then we will be using the .xsa generated in…

Table of Contents PYNQ Computer Vision An example Conclusion PYNQ According to webpage, PYNQ is an open-source project from AMD that makes it easier to use Adaptive Computing platforms. Nowadays, there are support for a wide variety…

Hardware Training Summary Lesson 4: Peripherals Zynq MPSoC General connectivity PS IO : MIO only Qual SPI NAND GEM - Gigabit Ethernet USB2.0 through ULPI interface GPIO : 0-2 Bank EMIO/EMIO Possibility SD/SDIO/eMMC Control…

What is Vivado IDE to Synthesize and Analysis of HDL/Verilog Language A single tool to Write, Compile, Simulate and Program Hardware Training Summary Lesson 2: The Case for a System-on-Chip Case for SoC : Why do we need SoC Processor…

In the Second Blog , I mentioned how to create a minimalistic hardware design based on Vivado. As mentioned in the First Blog , This blog post will be focussed on Petalinux. I will use the .xsa file from the minimalistic hardware design generated in the…

As mentioned in the First Blog , this blog will be focussed on Vivado based HW design. I will be writing about my experience in creating a simplest/minimalistic hardware design with the least amount of peripherals that is sufficient to do a SD card boot…

I am very grateful to element14 for giving the opportunity to participate in the Path to Programmable 3 design contest. I will be participating in the ultra96v2 track. I might be a bit late to join the party, but I have a lot of (exciting) things to share…

AMD Vitis unified software platform Some question with respect to AMD vitis unified development platform What is AMD Vitis unified development platform ? The Vitis unified software platform is an integrated development environment (IDE) for the…

Table of Contents The MAX7219 Peripheral The Software Result The MAX7219 Peripheral The MAX7219 IC is a "Serially Interfaced 8-Digit LED Display Driver", which interface is based on SPI, with an specific protocol for configuration and…