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Blog ZYNQ-SW Module 2 Minized Blog3 --lab6 & lab7
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  • Author Author: snidhi
  • Date Created: 19 Jan 2019 1:20 AM Date Created
  • Views 585 views
  • Likes 3 likes
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  • program fpga
  • fpga
  • minized
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Recommended

ZYNQ-SW Module 2 Minized Blog3 --lab6 & lab7

snidhi
snidhi
19 Jan 2019

The Module 2 of the MiniZed Path to Programmable is focused on software development in xilinx fpga. The previous minized SW development ZYNQ blog can be read here ZYNQ-SW Module 2 Minized Blog3 --lab4 & lab5

The Hardware related blogs are here Summary of Module 1 Path to Programmable ZYNQ HW blogs

The Software related blogs are here Summary of Module 2 Path to Programmable ZYNQ SW blogs

 

  • ZYNQ SW Module Lab 6
  • ZYNQ SW Module Lab 7
  • Conclusion

 

ZYNQ SW Module Lab 6

 

Aim: Developing Zynq Software with Xilinx SDK Lab 6 First Stage Boot Loader (FSBL)

 

Lab 6 Objectives:

 

• How to generate the FSBL

• What the FSBL application includes

• How to recognize some of the initialization sequences

 

What is FSBL?

First Stage Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures the FPGA with hardware bitstream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes A53/R5 out of reset. It supports multiple partitions, and each partition can be a code image or a bitstream. Each of these partitions, if required, will be authenticated and/or decrypted.

FSBL is loaded into OCM and handed off by CSU BootROM after authenticating and/or decrypting (as required) FSBL.

 

More reading Material on FSBL

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842019/FSBL#FSBL-WhatisFSBL

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841798/Build+FSBL

https://www.xilinx.com/video/soc/understanding-the-zynq-fsbl.html

 

This is my first time working with the xilinx FSBL and using the bootloader for zynq.

image

Using the standard template to run the xilinx FSBL

 

image

Building the xilinx FSBL

 

image

Looking into compiler settings for the Debug configuration

 

image

Understanding the main code of the FSBL

 

image

Fig: DDR Initialization Check  can be seen here

 

 

ZYNQ SW Module Lab 7

 

Aim: Developing Zynq Software with Xilinx SDK Lab 7 Boot from Flash

In this lab I created a boot image and boot an application from non-volatile memory. A complete boot-up requires at least three things:

1. FSBL

2. Bitstream (Optional)

3. Application

 

image

Using the Test_Peripherals application from previous development for booting from Flash memory

 

image

Creating a new boot image and set the output format to MCS

 

image

Setting up to program the Flash memory

 

image

Successfully programmed the flash memory

 

image

Testing with the serial port the results after booting from Flash memory

 

Conclusion

These two labs were quite useful as I learned to create boot image of an application and also boot the applicaiton from Flash memory Hardware. The instructions to run the create and run the boot image was clear in the tutorial and pretty easy to achieve.

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