AXI Interconnect PS PL on Zynq US+

Hi there,

The easiest way to have done this - especially since you are already using HLS - would have been to use SDSoC.  SDSoC handles all of the data movers for you.  In the design, you would only have needed to make a call to a function in your application code.

While I can offer suggestions to your design, ultimately this will get complex as you will need to work out the best solution.

• First determine the spirit in how you want your data to move in and out
• Next determine how much bandwidth you need
• Choose an AXI type that meets those needs
• Next implement that design as needed
  • The DMA is a bit complex to setup and I personally wouldn't want to attempt that over a forum - I would suggest if you need that, contact your local FAE for an assist

• From there, you mention Linux, so you will need to write a driver to access the memory that you assign within the Vivado design
  • That driver will (from a big picture) need to access the memory space you assigned to the AXI peripherals you assigned in Vivado, needs to handle interrupts from the AXI block, handle any other servicing that the AXI block you choose needs

Or, as I mentioned, migrate your HLS design into SDSoC, and you are essentially done.  SDSoC accepts all HLS pragmas and only has new SDSoC pragmas to help describe the spirit of the data movement.  The tool will choose the data movers, drivers/etc. that are necessary based on the spirit of what you describe.  Even without all of that detail, the tool is generally good enough to come up with a solution that will be good enough for one's needs.  This also means your design is portable to any other system that you have a platform defined.  Did I also mention, we maintain platforms for SDSoC so you do not even have to generate that?  That is, unless you need custom clocks rates /etc.

We actually have a load of training materials on this if you are interested.

Here is a link to the current offerings:

https://www.hackster.io/workshops/ultra96?ref=workshops

--Dan

For your reference:

HLS Pragmas for 2018.3 / 2019.1:
https://www.xilinx.com/html_docs/xilinx2018_3/sdaccel_doc/hls-pragmas-okr1504034364623.html#okr1504034364623

https://www.xilinx.com/html_docs/xilinx2019_1/sdaccel_doc/hls-pragmas-okr1504034364623.html#okr1504034364623

SDS Pragmas for 2018.3 / 2019.1:

https://www.xilinx.com/html_docs/xilinx2018_3/sdaccel_doc/sds-pragmas-nmc1504034362475.html#nmc1504034362475

https://www.xilinx.com/html_docs/xilinx2019_1/sdaccel_doc/sds-pragmas-nmc1504034362475.html#nmc1504034362475

Hi,

I am doing the same thing, where I want the PL to perform some action based on the data from the PS and send the data back to the PS.Also, when I connect the PL to the PS, i get the following errors.

1. ERROR: [#UNDEF] No clk source specified for /ps8_0_axi_periph/s00_couplers/auto_ds/M_AXI, when I try to connect the PS clock to it I get net interface errors.

2. ERROR: [BD 41-237] Bus Interface property ID_WIDTH does not match between /ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM0_FPD(16)

The ID width of both of these are read only hence I can never change them.

I will also attach the image , Please let me know if any changes can be made.

- Will i need BRAM for the same?

Hi Praseetha,

I don't see the image you say you attached, so I can't comment on the correctness of your block design.

Are you also targeting the UltraZed SOM mated to the I/O carrier?  If so, you might want to use a known-good design as an example to examine the AXI interconnect and clock connections, etc.  You can use the instructions in this Avnet HDL git HOWTO (Vivado 2020.1 and earlier)  blog to build a known-good Vivado hw platform for Avnet SOMs and SBCs.  This blog admittedly needs to be updated for recent changes we have made on the 2020.2 branch of the git repository, but in general the instructions should still get you what you need.

--Tom

Hi Tom,

No I am trying to connect a PL that I created on Vitis HLS, to the zynq ultra scale MPSOC. When I add both of them and simply click run automation , I get the following errors.

1. ERROR: [#UNDEF] No clk source specified for /ps8_0_axi_periph/s00_couplers/auto_ds/M_AXI, when I try to connect the PS clock to it I get net interface errors.

2. ERROR: [BD 41-237] Bus Interface property ID_WIDTH does not match between /ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM0_FPD(16)

Hi Tom,

No I am trying to connect a PL that I created on Vitis HLS, to the zynq ultra scale MPSOC. When I add both of them and simply click run automation , I get the following errors.

1. ERROR: [#UNDEF] No clk source specified for /ps8_0_axi_periph/s00_couplers/auto_ds/M_AXI, when I try to connect the PS clock to it I get net interface errors.

2. ERROR: [BD 41-237] Bus Interface property ID_WIDTH does not match between /ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM0_FPD(16)

Hi there,

*-*-*-*

As Tom mentioned, you probably want to take a look at how we set things up.  There are a LOT of configurations that you need to setup and as I suggested to the original user, if you are not familiar with AXI or working at that level of hardware, Vitis might be better for you.  It handles all the interconnect and data movers for you.  The simplicity is you only need to add in XLCONCAT blocks for interrupt feedback to the PS and "Processor System Reset" blocks.  From there, define the resources the tool is allowed to use and hit go.  You can grab our code from the Avnet repos and download that.  Run the make scripting and you will be able to see all the pieces that we put into place.  A shortcut can be taken if you look at the following link, where you can see what we do to "add" Vitis/SDSoC capabilities:

https://github.com/Avnet/hdl/blob/2020.2/boards/u96v2_sbc/base/u96v2_sbc_base.tcl#L546

http://github.com/avnet/[repo]

where [repo] is all 4: bdf, hdl, petalinux, vitis

Make sure you use the correct tag/branch!  Also note that as of this post the 2020.2 branch is not stable.

All that being said, I am not aware of the exact details of HLS's needs, as we use Vitis to avoid this very problem.  HLS's needs can be VERY custom depending on what you are specifically doing.

Have you been through the HLS user guide?

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1399-vitis-hls.pdf

Maybe that can help you?

*-*-*-*

For your second error, you have a bus width mismatch.  The AXI is defined to be 1 size and everything MUST comply.  If you do not have a bus that is of the same width it will not bolt up properly.

Think of the issues connecting bus(0 upto 127) and connecting it to a bus2(0 upto 15) or even bus3(15 downto 0), they will mismatch.  You would need to adapt to the hardened AXI as the multiples of it's configuration do not change.  In the case of AXI, you would need to use AXI Data Width Converters.

More details of your particular AXI needs can be found in the datasheet for the IP.  Double click the IP, then click on the Documentation button in the upper left of the Re-customize IP menu.

I cannot locate the documentation, but I think it is multiples of 32, and here is an example of what we have setup for Ultra96V2.  Here is a screen capture of the M_AXI_HPM0_FPD for the Ultra96V2 design:

ALL of even THAT being said...if you are not familiar with this flow, I believe it would really help to just use Vitis.  It's ability to handle all that interconnect is really it's power and in the time it took to reply to this, you might have already been up and running!  Once you have your platform setup, it really is that fast.  I've done demonstrations where I retargeted solutions to all of our platforms as fast as I could click the mouse.  The tools take care of creating/linking/setting up all of the data movers.

Hope that helps you out!

--Dan

Hi Daniel,

Firstly Thank You so much for explaining all of this.

The board that I am using is https://www.xilinx.com/products/boards-and-kits/zcu104.html.

I have used Vitis HLS to configure the saxi_0 IP:

Code

#include <stdio.h>

void saxi(char a, char b, char c)

{

#pragma HLS INTERFACE s_axilite port=a bundle=BUS_A

#pragma HLS INTERFACE s_axilite port=b bundle=BUS_A

#pragma HLS INTERFACE s_axilite port=c bundle=BUS_A

#pragma HLS INTERFACE s_axilite port=return bundle=BUS_A

c += a + b;

return ;

}

#include <stdio.h>

void saxi(char a, char b, char c);

int main()

{

  char a;

  char b;

  char c;

  char d;

  char sw_result;

  printf("HLS AXI-Lite Example\n");

  printf("Function c += a + b\n");

  printf("Initial values a = 5, b = 10, c = 0\n");

  a = 5;

  b = 10;

  c = 0;

  d = 0;

  saxi(a,b,c);

  d += a + b;

  printf("HW result = %d\n",c);

  printf("SW result = %d\n",d);

  if(d == c){

    printf("Success SW and HW results match\n");

    return 0;

  }

  else{

    printf("ERROR SW and HW results mismatch\n");

    return 1;

  }

}

This is not my actual project but I am trying to configure the connection on something small first before I do the connections for my code.

1. If I understand you correctly, You are telling me to write a code for all the connections is that correct ? including the PS , DRAM, and everything can be written on vitis HLS?

My initial plan was to create PL on vitis HLS and configure it with the PS on vivado.

2. If I can write the entire connection on vitis HLS as per the github link you have provided, can this be used for a zynq board as well ? Or do you have the code for this board

https://www.xilinx.com/products/boards-and-kits/zcu104.html.

3. I need to design a system where the input data comes from the PS, the PL does the computation and the result is transferred back to the PS. Can all of this be written on vitis HLS?

As of now I have a working IP, which performs the intended task on PL. (again this is a code explaining my pragma directives that i have used but not my intended task)

Thank You for your support!

Hi there,

You should probably ask for assistance on the ZCU104 over at the Xilinx.  They can most likely help you more than I can on that.

https://forums.xilinx.com/t5/Forums/ct-p/XlnxProd

1. What I suggested is you will need to look at the errors and solve them.  I tried to guide you somewhat, but really using a tool like Vitis would solve the problem in my opinion.
2. The link I provided shows you what we do with Designed By Avnet boards.  We do not support Xilinx boards.  Xilinx has a full support structure in place for that.  I am not sure what other pieces you have, but you are better off getting Xilinx support as their BSP, Vitis Platforms/etc. potentially has differences that would conflict with the support that I posted a link to
3. Vitis is designed to allow for custom accelerators and if you go through any Vitis training, I think you will see that what you described is very possible and in fact is the general use case.  I believe that everything you are asking for can be handled in Vitis as Vitis sits on top of HLS and uses the HLS tool for the C to RTL conversion, then generates the data movers and weaves it all together for you - based on what you have described

--Dan

Hi Dan,

Yes I am aware that xilinx has a fourm team, but I have been writing to them for weeks now and have not got any response from them. If you do have any documents for vitis which explains how we can configure the PL and PS the way i need for a zcu104 board it would be very very useful. will there be a HLS code for the zcu104 board similar to the code you have written for the Avnet board or is that something I will need to write from scratch ? As i am only a student I do not have much access , and I am only starting off with SOC. So, any help will be very useful.

Thank You

Praseetha

Hi there,

As I suggested before, I don't work with the ZCU104.  I don't have documentation on it.  Avnet's code does not target that device, so I really can't help you with that.  Xilinx has ZCU104 code in their Github/downloads page.  You should be looking at that.  The correct path is the Xilinx forums or your Xilinx FAE.  I just honestly do not have materials that target a ZCU104.

Second, we do not have any HLS code in the respect of what you are talking about.  The code we have is targeting Vitis in a way that SDSoC used to be targeted.  While HLS is used, we did not specifically write HLS, we used C and allowed the Vitis (SDSoC) portion of the tool to work out what it needed to do.  Which involved the tool choosing HLS and the tool choosing what data movers to put into place.  To be totally open about this, I have never attempted to implement HLS in the way you are suggesting.  It is very complex and unnecessary when Vitis will do all of that for you in a matter of seconds.  Since you are using a ZCU104, Xilinx has a Vitis platform.  You should be able to just use that without any effort on your end.  You will need to check Xillinx's Github / Download pages for that.

if you cannot target Vitis, and are stuck on pure HLS, you will need to go through Xilinx's training materials.  I do not have anything on just HLS, as this is a very large topic.  More than someone can hope to explain in a forum post or the types of trainings that my group tends to target.  It is similar to you asking how to write C or Verilog or VHDL.  There are many online support paths for this, but for HLS and a ZCU104, this is not it. I cannot post the link, but if you search the web for "vitis hls training" you will see many sources of assistance.  There are paid and free options.  Adam Taylor has a good series on various HLS like topics.  I know he is a fan of HLS and has quite a few articles that are free, but tend to lack the details you seemingly want/need.

I am sorry that I cannot help more than I have above.

--Dan