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Avnet Boards General Maximum frequency inputs of Zedboard PMODs
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Related

Maximum frequency inputs of Zedboard PMODs

longgang
longgang over 5 years ago

Hi, I am new to the Zedboard. I want to use an ADC with SPI 5MHZ throughout, which means SDO will reach to around 100MHZ  with 16bits. Then, I want to use PMODS JA-JD to receive the data from the ADC. What worries me is that could Zedboard PMOD pins are available to receive such inputs with 100 Mhz?  I know the I/O banks of FPGA in the PL side can reach 2-4 times of the main clock, but here the problem is the path from Zedboard Pmod pins to the PL GPIO blocks.

 

Could someone help me? Thanks so much!!

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  • michaelkellett
    michaelkellett over 5 years ago +1
    What ADC are you planning to use ? You need to look very carefully at the timing margins - frequently ADCs have "keep out " times which will push the clock frequency up and may not work well with standard…
  • drozwood90
    drozwood90 over 5 years ago +1 verified
    Hi there, On Zedboard, the limit is going to come up in the connector. It is not a high speed connector. A quick Google search and you should be able to locate the PMOD specification. It is maintained…
  • longgang
    longgang over 5 years ago in reply to drozwood90 +1 suggested
    Hi Dan, Thanks for the reply. I think this is what I am looking for. I read through the hardware user guider of Zedboard. It only mentions that the JC1 and JD1 support 525Mhz LVDS, but no information about…
Parents
  • michaelkellett
    0 michaelkellett over 5 years ago

    What ADC are you planning to use ?

     

    You need to look very carefully at the timing margins - frequently ADCs have "keep out " times which will push the clock frequency up and may not work well with standard SPI.

     

    Are you planning to write your own SPI interface code ?

     

    MK

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  • longgang
    0 longgang over 5 years ago in reply to michaelkellett

    Hi MK

     

    Thanks for the reply. The ADC I am planning to use is LTC2323-16.  In this datasheet, It said:" A 105MHz external clock must be applied at the SCK pin to achieve 5Msps throughput". Thus, the SDO frequency will be higher than the sample rate.

     

    I know there is an SPI AXI IP that can be controlled by PS. But for the high-speed application, the latency in the PS SDK code will become a problem. Maybe the only  way to achieve that is to write an SPI interface in VHDL/Verilog.

     

    Longgang

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  • michaelkellett
    0 michaelkellett over 5 years ago in reply to longgang

    You will definitely have to write your own interface code.

    If you use the LVDS interface via the FMC connector you still have to observe timings like tDCNVSCKL, pages 5 and  21 of the data sheet.

    Standard SPI interfaces won't do this (or the LVDS signalling).

    The physical design of the board will be a challenge too.

    I've used similar parts, single ended not LVDS - it took us two board spins to get it to work and one more to get it to work over an extended temperature range.

    We had the FPGA and the converters on the same board.

     

    You might like to consider using ADCs with // outputs -  TI do a 5MHz sampling part.

     

    MK

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  • michaelkellett
    0 michaelkellett over 5 years ago in reply to longgang

    You will definitely have to write your own interface code.

    If you use the LVDS interface via the FMC connector you still have to observe timings like tDCNVSCKL, pages 5 and  21 of the data sheet.

    Standard SPI interfaces won't do this (or the LVDS signalling).

    The physical design of the board will be a challenge too.

    I've used similar parts, single ended not LVDS - it took us two board spins to get it to work and one more to get it to work over an extended temperature range.

    We had the FPGA and the converters on the same board.

     

    You might like to consider using ADCs with // outputs -  TI do a 5MHz sampling part.

     

    MK

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  • longgang
    0 longgang over 5 years ago in reply to michaelkellett

    Hi MK,

     

    Thanks for the reply. For the LVDS, the PCB design will be really hard since the differential path should be strictly identical. Also, the reposition of the DCLK with DATA is needed owing to delay during the transition. (Using IDEALY2 and  ISERDESE2  of FPGA banks). That will be a huge challenge for a new learner :-(. I will start with a parallel  ADC as a first step.

     

    LONGGANG

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  • michaelkellett
    0 michaelkellett over 5 years ago in reply to longgang

    Hello Longgang,

     

    Take a look at

    ADS1606 from TI, I haven't used it yet but I have a plan to.

     

    MK

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