Hi, I am new to the Zedboard. I want to use an ADC with SPI 5MHZ throughout, which means SDO will reach to around 100MHZ with 16bits. Then, I want to use PMODS JA-JD to receive the data from the ADC. What worries me is that could Zedboard PMOD pins are available to receive such inputs with 100 Mhz? I know the I/O banks of FPGA in the PL side can reach 2-4 times of the main clock, but here the problem is the path from Zedboard Pmod pins to the PL GPIO blocks.
Could someone help me? Thanks so much!!