Access upper 16 MB of QSPI Flash

Spansion has been working on validating this with the Zedboard and the S25FL-S flash that come with this board, and we have shown it is definitely possible in certain circumstances.

In Linear mode the QSPI controller is definitely limited to 24b addressing, although it is possible to switch the bank register so this mode can access the higher banks.

But for Linux and u-boot the QSPI IO mode is more appropriate. In our prototype u-boot code we used the bank address register to enable addressing to span >128Mb (16MB) address space. All legacy flash commands with 3B addressing are proven to work correctly for multi-IO operations, and any single-IO command can also work (the new flash commands expecting 4B address all work with QSPI so long as they are single-IO).

In our discussions with Xilinx we've learned that the flash extended address register can be used to enable 4B address arguments for the legacy READ commands that normally expect 3B addresses; this works so long as the QSPI controller is configured to expect an extra dummy byte. This is a cleaner way to support extended addressing for single and multi-IO reads.

Linux MTD support is a work in progress, but we're expecting to have sample code pretty soon.

Let me know if you are interested in seeing the sample code we have so far.

Thanks for the info Max.  Sounds like you guys are definitely working the issue.

We have a Zynq Z-7045 design in the works.  The PL configuration file alone is over 12 MB, so there's no way that'll fit in 16 MB address space along the Linux image/ramdisk.  I'm trying to avoid using up the MIO pins for QSPI_1 just to gain the additional 16 MB for QSPI boot.

The approach I'm trying to go with is boot into Linux using the lower 16 MB, and then switch to the upper 16 MB, read the configuration file and then configure the FPGA with xdevcfg.

I'm hoping you guys and Xilinx can work out this issue so that Linux MTD is supported.  Thanks!

Hi to everybody.
Has been there any change in the QSPI code to support more than 16 MB yet?
Thanks and best regards,
Giulio

Any resolution to this?

Latest kernel drivers seem to be able to cope with more than 16 MB of flash.
http://forums.xilinx.com/t5/Embedded-Linux/zc702-QSPI-Flash-Options-16-or-32-MB/m-p/268668

Still there is a problem reguarding the reboot that should be taken into account.
http://forums.xilinx.com/t5/Embedded-Linux/Reboot-problem-when-QSPI-is-in-quad-I-O-mode/m-p/355079

Regards,
Giulio

Any resolution to this?

Thanks in advance

I think support fo 32 MB has been added lately.

http://forums.xilinx.com/t5/Embedded-Linux/zc702-QSPI-Flash-Options-16-or-32-MB/m-p/345675#M6645

http://forums.xilinx.com/t5/Embedded-Linux/Reboot-problem-when-QSPI-is-in-quad-I-O-mode/m-p/384851#M7317

Still the user should be careful in designing an appropriate reset line to the flash device in order to reset it at its default state when rebooting.

Best regards,
Giulio

Hi Josu00E9 - We submitted our draft code to Xilinx some time ago, and they have integrated our prototyped approach into their code base. So you just have to download the latest Linux snapshot from Xilinx to get full support for SPI addressing. As mentioned earlier in the thread, the software uses SPI commands with 3 byte addressing and uses the bank address register to access other banks. Full addressing support is also provided in the Xilinx programming tools as well. So just get the latest from Xilinx, and you'll be good to go.

Best Regards,
Max

Thank you. I have detected my s25fl256s1 with 256Mb. Perfect with Linux-xlnx-3.12 from xilinx

Can you tell me where is the detailed tutorial about how to access upper 16 MB of QSPI FlashuFF1Fthank you very much!