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Partial Reconfiguration for the Zedboard

Former Member

Hi Forum,

I was wondering if anyone has managed to complete a partial reconfiguration (PR) project with the zedboard, specifically having the PL completely reprogrammed with the PS and a stand-alone OS.

So far I have managed to generate full and partial bitfiles and program the board just using impact. I fall on my face, however, when I attempt to code something in the Stand alone OS through SDK. To test I convert the partial bitfiles into bin files and use the XMD to store it in the DDR. I then found some code regarding the Zynq on the Xilinx forums for programming the fabric with the stored bin file.

Has anyone successfully managed to do this?

Thanks

  • 0

    Hi,

    I am also trying to bring up a Partial ReConfiguration design that can be controlled from Linux and load bit files dynamically.

    I am waiting for the XAPP115 from Xilinx, to get idea on loading the bit files to DDR through FSBL.

    Let me know if you followed some guide or tutorial for this.

    Thanks,
    Anup.

  • 0

    Hi,

    I have been trying using XDM to downmoad bin files into DDR but never success, can you share with me your method to download bin files into DDR?

    Thanks so much!!!

    Tian

  • 0 in reply to Former Member

    Yeah, Sorry for not responding sooner. There are a few ways you can get the .bin onto the DDR.

    Open the XMD
    1. You can open the XPS/EDK, Debug > Launch XMD
    2. You can open up the XMD through the SDK, if you do this in debug mode it appears as a tab window in the upper right corner

    Program the Bin File
    dow -data myfile.bin 0x00200000

    Obviously you need to make the address within the address range of your DDR.

    You can have the bin file placed there with the device initialization as an alternative option

    1. Right click on your project, Run As > Run Configuration
    2. Click on the Device Initialization tab
    3. Add the .bin file and the address and it will do it automatically

    Sorry again for the late reply, send me a direct pm if you are having trouble

  • 0 in reply to Former Member

    Hi Anup

    XAPP115 is finally up, I haven't looked at it yet. I was not following a guide, but a series of forum posts about it in the Xilinx Forums, Search Zynq PCAP

  • 0

    Hey guys, Xilinx University Program has a curse for Partial Reconfiguration on Zynq.
    Enjoy ituFF1AuFF09

  • 0 in reply to Former Member

    I'm sorry but I can't find XUP PR materials on Zynq.
    The teaching materials is on XUP V5 board or ML605 board.
    Can you give some Links?

  • 0

    Hi all,
    I am also trying to reconfigure the PL from soft.
    I follow the steps described in the TRM. After I initiate a DMA transfer, the D_P_DONE_INT flag is set, meaning that "Both DMA and PCAP transfers are done for intermediate and final transfers". BUT, the DONE_INT flag (which means "DONE signal from PL indicating that programming is complete and PL is in user mode") is not set.

    TRM indicates that "The PCFG_DONE flag will not be set if the previous PL configuration was not cleared using PCFG_PROG_B". But I do clear the previous config.

    Is there more steps to do to program the PL after the DMA transfer is done?
    Does the bitstream have to be wrapped somehow? I am using the same bit file as the one I use when configuring the PL with SDK->program FPGA tool.
    Is there a means to check if data is correctly transferred?

  • 0

    Hi all,

    I had a hard time finding the XAPP mentioned above.  After some looking around, I found this XAPP1159 document:

    http://www.xilinx.com/support/documentation/application_notes/xapp1159-partial-reconfig-hw-accelerator-zynq-7000.pdf

    It is based upon the ZC702 TRD but should still be somewhat relevant to ZedBoard.

    Regards,

    -Kevin

  • 0

    Yes! It works now. Thank you zedhed.
    I've found what I was looking for on this page: http://wiki.xilinx.com/zynq-pr-rd

    The bitstream generated in PlanAhead cannot be used like that when configuring the PL through a PCAP transfer. It must be converted to a binary format. It's simply a TCL command to use:

    exec promgen -b -w -p bin -data_width 32 -u 0 yourbitstream.bit -o convertedbitstream.bin

    Note that "-data_width 32" forces the file length to be a multiple of 4 bytes, as source length and destination length are  the "Total number of 32-bit words in the PL bitstream" for a PCAP transfer.

    I haven't read entirely the link mentioned above, but it seems really interesting.

  • 0

    Hi all !! I'm beginner with Zedboard and trying to test partial reconfiguration function on the Zedboard. My design for testing is very easy.
    - I designed counter and use the button to control the counter. Every time hitting the button, counter will increase 1 or decrease 1.
    - The counter module is the partial reconfigurable module with function count up and count down. In my design i just used PL for partial reconfiguration and Impact to download the bitstream (no PS).
    I built the PlanAhead project and generate the full bit stream and partial bit stream for the counter module. when I downloaded (by Impact) the full bit stream of count up module it works ok but when i try to download the partial bit stream to change the counter function from count up to count down, the function doesn't change. Or when i downloaded the full bit stream for count down, the counter doesn't change either, it still counts up. I try to with many configuration options (imported, implemented, promoted) but it still doesn't change from count up to count down.
    My questions are:
    1. Can i check the partial reconfiguration function on this way.
    2. What issues in may design or i misunderstood something in partial reconfiguration function.
    Please give me your suggestion. i appreciate your help a lot.