What is the maximum current the MT3620 GPIOs pins can output?
All the pis provide the same current?
Can you configure any of the pins to have high drive strength (i.e 20-mA)?
What is the maximum current the MT3620 GPIOs pins can output?
All the pis provide the same current?
Can you configure any of the pins to have high drive strength (i.e 20-mA)?
Hi,clem57, thanks for the link.
I don't see any indication of high-drive GPIOs support in that repository,
nor at https://docs.microsoft.com/en-us/azure-sphere/hardware/mt3620-product-status,
nor at https://github.com/Azure/azure-sphere-samples
I only found this table at https://d86o2zu8ugzlg.cloudfront.net/mediatek-craft/documents/mt3620/MediaTek-MT3620-Product-Brief-Nov2018.pdf
Enrique
MT36230 GPIOs can be configured for higher drive strengths (per the MT3620 M4 Datasheet document which is available via NDA).
I recommend this type of question be asked on the MSDN Azure Sphere support forum, where specialist resources from Microsoft can advise, as configuring of output drive strengths is not currently accessible from Azure Sphere OS.
-Peter
Please provide the details when you have them javagoza. I am sure this is important to many folks like us.
it can not - MMU is enabled and protect direct access to rigesters... or securiy is not security
only BareMetal
I've posted a feature request at Azure feedback forum:
You can vote for it.
My understanding is that drive-strengths are configurable from the M4 code.
I'd suggest besides the OS feature request, also request support for the M4-based settings in the MSDN forum
This is "default" Mediatek GPIO structs for cortex-M4 ...
Try find offsets https://github.com/Azure/azure-sphere-samples/blob/master/Samples/GPIO/GPIO_RTApp_MT3620_BareMetal/mt3620-gpio.c#L19
struct {
volatile uint32_t RW[2];
uint32_t RESERVED[4];
}GPIO_DRV_REGISTER_T;
struct {
GPIO_REGISTER_T GPIO_IES;
GPIO_REGISTER_T GPIO_PD;
GPIO_REGISTER_T GPIO_PUPD;
GPIO_REGISTER_T GPIO_PU;
GPIO_REGISTER_T GPIO_R0;
GPIO_REGISTER_T GPIO_R1;
GPIO_RDSEL_REGISTER_T GPIO_RDSEL;
GPIO_REGISTER_T GPIO_SMT;
GPIO_REGISTER_T GPIO_SR;
GPIO_TDSEL_REGISTER_T GPIO_TDSEL;
}GPIO_CFG0_REGISTER_T;
struct {
GPIO_DRV_REGISTER_T GPIO_DRV; < ----- here is driving
GPIO_REGISTER_T GPIO_G;
GPIO_REGISTER_T GPIO_IES;
GPIO_REGISTER_T GPIO_PD;
GPIO_REGISTER_T GPIO_PUPD;
GPIO_REGISTER_T GPIO_PU;
GPIO_REGISTER_T GPIO_R0;
GPIO_REGISTER_T GPIO_R1;
GPIO_RDSEL_REGISTER_T GPIO_RDSEL;
GPIO_REGISTER_T GPIO_SMT;
GPIO_REGISTER_T GPIO_SR;
GPIO_TDSEL_REGISTER_T GPIO_TDSEL;
}GPIO_CFG1_REGISTER_T;
struct {
GPIO_REGISTER_2_T GPIO_DIR;
GPIO_REGISTER_2_T GPIO_DOUT;
GPIO_DIN_REGISTER_T GPIO_DIN;
GPIO_MODE_REGISTER_T GPIO_MODE;
}GPIO_BASE_REGISTER_T;