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Mosfet biasing or heat issue

Dig
imageimage
 
I am having an issue with a IXYS paired mosfet chip, FMP26). It is being switched at 1-2Mhz. A 12A driver, EL7158ISZEL7158ISZ, is delivering more current to the larger gate capacitance at higher frequencies. (Under 500khz not a concern.) A 10V output square wave at 1Mhz is applied to the mosfet gates.
 
As I gradually increase the voltage on the P channel source up to 50-60V, the mosfet gradually gets hot, and this is without a load on it.  Now this effect is reduced by lowering the resistor (100 ohm in attached figure) value which is biasing the gate, reduces VGS by creating DC offset on the gate which lifts the pulse waveform. I am not sure what is going on though and how to properly bias this as 100 ohms is very low.  Shouldn't I be able to switch it with these VGS?

Dig
 
Attached is the datasheet
Attachments:
imageDS100033A(FMP26-02P).pdf
  • 0

    Usually reverse polarized diodes are used across gate-source resistors to obtain DC offset and series gate resistors with parallel diodes to prevent ringing and cross-conducting. See schematics on page 6 http://img.chipfind.ru/pdf/zetex/zxcd50steval.pdf

  • 0 in reply to RWM

    RWM,

     

    Looking into your suggestion.

     

    Dig

  • 0

    First I will describe the ideal situation for switching a fet on and off. (See attached pictures.) At moment t1, the driver circuit is pushing a current of 1 Amp or more to the gate of the fet, to charge the gate – source and the gate – drain capacity. For short switching times, a high drive current is necessary. That’s why special driver IC’s can deliver high output currents. At moment t2, the fet will start conducting, causing the drain Voltage to drop from 60 V to zero. The gate – drain capacity will discharge, counteracting the rise in gate Voltage. At moment t3, the fet is completely turned on. The gate Voltage will rise to the maximum drive Voltage. When the fet is switched off, the same will happen. If the drain Voltage is higher, the time between t2 and t3 and between t6 and t7 will be longer.  When driving a half bridge, it is important that the upper and lower fet don’t conduct at the same time. When using an N-channel and a P-channel fet, this can be done with the same drive-signal, like shown in the picture at the bottom. As you can see the gate drive voltage for the upper device is measured from the top of the drive-pulse. Only if the maximum amplitude of the gate pulse is not too high, there will be a dead time between the conducting moments of the fets.  In a practical situation, the inductance of the traces on the board and the inductances of the capacitors used will cause ringing and oscillations. Ringing might cause the fets to conduct at moments we don’t want this. Keep the tracks between the driver and the fets short and place decoupling capacitors as close to the devices as possible. The 100 ohm resistors are to damp oscillations and prevent overshoot of the gate pulses.  Lowering the value of these resistors, for instance to 50 ohm, will further damp oscillations and lower the gate drive Voltage.

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  • 0 in reply to Dig

    Dig,

     

    do you have solved this problem? What is your solution?