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Quadrature Decoder with Logic Gates Circuit FPGA

juanes.pazj

I need to read two rotary quadrature encoders at the time I didnt know that the PSOC4 could work with the TCPWM Quadrature decoder but I really enjoyed this circuit It is a really good example of the digital logic power included on PSOC.

the great thing about this is that all the circuit logic is made via hardware that means there is no work required by the processor until it reaches the causes the interrupt. this way I won't waste processing power on this reading.

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here is a little simulation of how this works notice that on each case only one of the lights turns that would turn on the interrupt sequence for that pin.

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  • Thanks for posting - I do a lot of FPGA work but I don't use PSoCs,

     

    It's not a very FPGA like use of logic - (but may be perfectly sensible for the limited CPLD style logic in a PSoC).

     

    Why ?

     

    Well, almost all (possibly all)  FPGAs are designed for synchronous logic and this is an asynchronous design (the flip flop is clocked by the XOR of the two inputs). In a very simple design like this it may be OK (but you can't tell what will happen if the two inputs change simultaneously) - in real FPGAs the timing verification tools can't work with asynchronous designs - so they are avoided because you can never be sure that they will work.

     

    Do the PSoC tools offer simulation and any timing verification ?

     

    MK

  • in reply to michaelkellett

    Yes!

    There are clock domains on the PSoC and they can't be directly connected to standard logic connections. They have to be done properly in a controlled manner.

    An alternative to the above circuit is to incorporate Gray Code verification and suitable FSM (Finite State Machine) to ensure that one bit can change at any one time to change states.

     

    Surprisingly there are many consumer products that do not properly decode quadrature encoded switches. If you spin them to fast the product can get quite confused even incrementing in the wrong direction.

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  • in reply to michaelkellett

    Yes!

    There are clock domains on the PSoC and they can't be directly connected to standard logic connections. They have to be done properly in a controlled manner.

    An alternative to the above circuit is to incorporate Gray Code verification and suitable FSM (Finite State Machine) to ensure that one bit can change at any one time to change states.

     

    Surprisingly there are many consumer products that do not properly decode quadrature encoded switches. If you spin them to fast the product can get quite confused even incrementing in the wrong direction.

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