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Forum Is the Gizmo2 suitable for high speed data acquistion?
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  • State Suggested Answer
  • Replies 9 replies
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  • high_speed_data_acquisition
  • fpga
  • gizmo2
  • adc
Related

Is the Gizmo2 suitable for high speed data acquistion?

Former Member
Former Member over 10 years ago

Hello.

My area of interest is high speed data acquisition.I'd like to connect a quad or octal high speed ADC (serial LVDS output) running at speeds from say 25 MSPS to 125 MSPS per channel.

For the quad serial LVDS output ADC , need about 20 output lines. I saw on the following link (http://www.gizmosphere.org/wp-content/uploads/2014/11/AMD_GIZMO2_Development_Board_Schematic.pdf) a block diagram of the Gizmo2, which appears to have only 8 GPIO lines.

wonder how it might be possible to use the PCIe edge connectors or SATA connectors to interface the ADC to the Gizmo2.

Maybe it's simply not possible to interface such ADCs directly to Gizmo2 and instead will require a seperate FPGA board, some high speed ADC board custom design to interface with the FGPA board and then try and interface the combined FPGA + ADC  module to the Gizmo. Getting rather complicated.

I would appreciate your thoughts on this please.

Thanks.

Regards,

Will.

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  • element14support
    0 element14support over 10 years ago

    Hello wf215

    Welcome to the element14 Community, we hope you enjoy it! I will move this over to the Single-Board Computers area as it is a better fit.

     

    Thank you,

     

    Jamie

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  • michaelkellett
    0 michaelkellett over 10 years ago

    An 8 channel ADC at 125Ms/S = 1Gbyte/S at 8 bits or 2 Gbyte/S at 16 bits. That's equivalent to one or two 10Gbit Ethernet ports - you are not going to make sense of this amount of data (or do anything with it) with a tiny processor like the Gizmo.

     

    About the only way to get this amount of data from ADC into memory and then computer is by using an FPGA for the glue and multi-lane PCIe or possibly multiple 10Gbit ethernet ports.

    At the bottom end of your speed range it's only 200Mbyte/S - still too much for tiny processors and Gbit Ethernet but easier on PCIe or possibly UltraSpeed USB. At this lower rate SATA is possible but difficult - because now your ADC and FPGA have to pretend to be a disk drive.

     

    Think in terms of medium size FPGA, more than £10k on FPGA design tools, buying in some IP for UltraSpeed USB or Gbit Ethernet and  2000 hours of development effort.

     

    If you only want one just buy it. https://www.picotech.com/oscilloscope/4824/8-channel-oscilloscope

     

    If you want to pay for a  design ..............

     

    MK

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  • Former Member
    0 Former Member over 10 years ago in reply to michaelkellett

    Thank you MK for those comments. Makes sense.

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  • Robert Peter Oakes
    0 Robert Peter Oakes over 10 years ago in reply to Former Member

    Gizmo 2 is more like a small Windows or Linux PC, more abilities than a PI but mot as much as a full blown PC

     

     

     

    So for fast data accusation it would depend on what “FAST” is. As there is a multi tasking OS that will make it difficult to maintain critical timing

     

     

     

    You may want to use an Arduino or Launchpad type device as the capture device and the Gizmo as a very powerful HUB providing security, aggregation and analysis for the collected data

     

     

     

    Peter

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  • clem57
    0 clem57 over 10 years ago

    If you really want to play with these speeds, I recommend the Mojo FPGA package as a relatively low cost yet capable processor. Usually with that rate, a trigger should be setup to record only the necessary data or output it as a scope. @wf215 please let us know how you go with this interesting project

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  • Former Member
    0 Former Member over 10 years ago in reply to clem57

    Thank you all for your comments and suggestions. Much appreciated.

    W.

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  • michaelkellett
    0 michaelkellett over 10 years ago in reply to clem57

    The OP wants to run his ADCs at 125 Msamples per second - that's a minimum of 1Gbit/s per ADC and he wants 8 of them. The Mojo is a simple low cost FPGA board and doesn't have the necessary high speed impedance controlled IO to connect to this kind of ADC,

    The FPGA on the Mojo is a low end cheapy - moving Gbytes of data per second takes a bit more than that.

     

    @Peter,

     

    The OP defined FAST - and at speeds of the order of 1GBbyte per second it's out of Arduino, Launchpad or Gizmo range.

     

    MK

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  • clem57
    0 clem57 over 10 years ago in reply to michaelkellett

    He will need more than 1 board I admit!

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  • michaelkellett
    0 michaelkellett over 10 years ago in reply to clem57

    It'll be worse than that - it isn't easy to pipe 1GHz LVDS from an ADC to an FPGA though any kind of connector. The connectors on the Mojo won't do it.

    Using multiple FPGAs to gain performance is usually only worth doing when you've run out of the performance you can get on one FPGA.

     

    A typical high speed data acquisition architecture would have the ADCs connected directly to the FPGA and as close to it as possible, the FPGA will need a buffer memory which could be 32 bit wide DDRAM. You need to budget for  a memory bandwidth about three times that of the ADCs if you want to stream and about 1.5x if you just want to capture and then read. So that's 750MHz data rate for streaming or a modest 400MHz for capture.

     

    To get the data out of the buffer you'll need an interface that can sustain 1Gbyte/s for streaming (10Gb Ethernet ?)  or less if you just need to read the data in non real time (USB3 ?).

     

    It's a difficult job - in my first post I didn't mention the scope/logic-analyser you would need to get this working - think £20k minimum, but more likely up to £50k.

     

    I'm planning a more modest system for  a client - 2 or 4 channels (not sure yet) 8bit, 50 - 100Msamples/sec, capture only, some real time processing on the FPGA, Gbit Ethernet control/data interface.

    It'll need a custom board, will use 64 bit data path to ram, probably a Lattice ECP3-70 FPGA but we will consider a switch to Xilinx.

     

    MK

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