Hi, I'm a total eagle beginner, and I've just made my first schematic and board. Could you please check it, if it's usable? Thanks 
Hi, I'm a total eagle beginner, and I've just made my first schematic and board. Could you please check it, if it's usable? Thanks
On 20.07.2015 00:56, Jacob Sycha wrote:
Hi, I'm a total eagle beginner, and I've just made my first schematic
and board. Could you please check it, if it's usable? Thanks
First impressions:
-Double sided board seems overkill for this simple circuit. See if you
can make it single layer.
-Track thickness is very thin. Thin tracks are harder to manufacture.
-You can probably compress pcb size to a minimum.
-Wire bends are a bit untidy.
-For schematic, there is alot of unnecessary junctions. There is no need
for junctions at pin connections, or at 90deg bends.
-The 555 timer seems to already exist (several times) in Eagle libraries
A more critical look:
-I opened this is eagle 6.5.4, and I ERC errors:
-consistancy error :net class parameters differs in brd vs sch
-consistancy error :LED naming different in brd vs sch
-U1 pin 5(CONT) is defined as an input but doesnt have any input (this
could mean the U1 could go nuts, or library component pin direction for
pin 5 is wrong). Taking a quick look at the datasheet, I'd suggest
putting a capacitor on this pin to gnd, but I do not know this circit.
Since I'm unsecure, I would just put it in and worry about soldering it
later.
ERC Warnings:
-Missing juction at the CONN xref
-VDD power pin of U1 connected to N$1 (Eagle expects pins with direction
POWER to be connected to a net with same name as the pin)
-LED1 is missing a value
DRC issues:
-For this kind of board, I would make larger distance between pads and
wire (fill).
-There are some weird stuff left on stop mask around pin 4 of U1. It
seems to be in the package definition.
-Capacitor package has capacitor symbol on pads. They will be shaved off
by the manufacturer but if you do want silk screen, I'd remove it from
package.
Finally, I have a personal preference for SMD components for small
projects. Drilling is just unnecessary work, and soldering SMD runs
smooth after some practice. Im sure you can find tutorials on youtube.
I also prefer to have sensible netnames that can quickly point you back
to schematic when reviewing the layout.
I did some homework for you and attached the cleanup I did to your
project. Compare it with yours 
Use 7zip.org to unpack.
Am 20.07.2015 um 09:22 schrieb Morten Leikvoll:
On 20.07.2015 00:56, Jacob Sycha wrote:
Hi, I'm a total eagle beginner, and I've just made my first schematic
and board. Could you please check it, if it's usable? Thanks
First impressions:
-Double sided board seems overkill for this simple circuit. See if you
can make it single layer.
-Track thickness is very thin. Thin tracks are harder to manufacture.
-You can probably compress pcb size to a minimum.
-Wire bends are a bit untidy.
-For schematic, there is alot of unnecessary junctions. There is no need
for junctions at pin connections, or at 90deg bends.
-The 555 timer seems to already exist (several times) in Eagle libraries
A more critical look:
-I opened this is eagle 6.5.4, and I ERC errors:
-consistancy error :net class parameters differs in brd vs sch
-consistancy error :LED naming different in brd vs sch
-U1 pin 5(CONT) is defined as an input but doesnt have any input (this
could mean the U1 could go nuts, or library component pin direction for
pin 5 is wrong). Taking a quick look at the datasheet, I'd suggest
putting a capacitor on this pin to gnd, but I do not know this circit.
Since I'm unsecure, I would just put it in and worry about soldering it
later.
ERC Warnings:
-Missing juction at the CONN xref
-VDD power pin of U1 connected to N$1 (Eagle expects pins with direction
POWER to be connected to a net with same name as the pin)
-LED1 is missing a value
DRC issues:
-For this kind of board, I would make larger distance between pads and
wire (fill).
-There are some weird stuff left on stop mask around pin 4 of U1. It
seems to be in the package definition.
-Capacitor package has capacitor symbol on pads. They will be shaved off
by the manufacturer but if you do want silk screen, I'd remove it from
package.
Finally, I have a personal preference for SMD components for small
projects. Drilling is just unnecessary work, and soldering SMD runs
smooth after some practice. Im sure you can find tutorials on youtube.
I also prefer to have sensible netnames that can quickly point you back
to schematic when reviewing the layout.
I did some homework for you and attached the cleanup I did to your
project. Compare it with yours
Use 7zip.org to unpack.
Hi Morton,
despite the fact that you are verrrrry polite 
here my critics to your layout:
for though hole technology the bottom layer should be used
and you "confirm" his way of connecting the gnd connections via ratsnest.
This method leads imho to coincidental connections specially in higher
density layouts.
--
Mit freundlichen Grüßen / With best regards
Joern Paschedag
On 20.07.2015 10:15, Joern Paschedag wrote:
Hi Morton,
despite the fact that you are verrrrry polite
here my critics to your layout:
Hey, and thanks for giving feedback 
I really appreciate it starting
to think I can do it all.
for though hole technology the bottom layer should be used
Yes you are right I should have moved all to bottom layer for this
design. My excuse is mostly being in "smd" mode 
For thorugh hole, its
easier to solder at the bottom, away from components. But signal wise,
of course it doesnt matter if you put this on top or bottom of the real
pcb. If you choose top, you have to make sure there is solder stop or no
unwanted exposed metal between top and components.
Tbh, I dont know if you can put eagle to single layer mode on L16 and
avoid the top mask vs silk DRC issues. Maybe you do?
and you "confirm" his way of connecting the gnd connections via ratsnest.
This method leads imho to coincidental connections specially in higher
density layouts.
Doing filled routing on layouts that doesnt have a separate solid signal
layer may be an issue yes. But for this brd, the GND is rather easy to
get an overview over. For a slightly larger board, I would have second
thoughts without the full GND backup and maybe done a GND backbone wired
thick and filled over just for the nice look (and less copper to etch off)
Am 20.07.2015 um 10:52 schrieb Morten Leikvoll:
On 20.07.2015 10:15, Joern Paschedag wrote:
Hi Morton,
despite the fact that you are verrrrry polite
here my critics to your layout:
Hey, and thanks for giving feedback
I really appreciate it starting
to think I can do it all.
for though hole technology the bottom layer should be used
Yes you are right I should have moved all to bottom layer for this
design. My excuse is mostly being in "smd" mode
I was certain of that!!!
For thorugh hole, its
easier to solder at the bottom, away from components. But signal wise,
of course it doesnt matter if you put this on top or bottom of the real
pcb. If you choose top, you have to make sure there is solder stop or no
unwanted exposed metal between top and components.
Tbh, I dont know if you can put eagle to single layer mode on L16 and
avoid the top mask vs silk DRC issues. Maybe you do?
I dunno, never done single layer...
and you "confirm" his way of connecting the gnd connections via
ratsnest.
This method leads imho to coincidental connections specially in higher
density layouts.
Doing filled routing on layouts that doesnt have a separate solid signal
layer may be an issue yes. But for this brd, the GND is rather easy to
get an overview over. For a slightly larger board, I would have second
thoughts without the full GND backup and maybe done a GND backbone wired
thick and filled over just for the nice look (and less copper to etch off)
Yes, for this board it's peanuts...
But I remember some faulty boards I had to check...
Schematics were OK but still didn't work.
The boards carried some higher currents, where the gound wasn't as
straight as the positive supply. Instead gnd was scattered through an
"asteroid field" (components)
And every time I heard:"I'm doing it since years that way" (gnd
connections via ratsnest)
A simple straight wire proved this fault.
Anyway I just wanted people not to adapt this method as a "standard" to
avoid trouble.
--
Mit freundlichen Grüßen / With best regards
Joern Paschedag
