Is there a way to systematically insert ICT testpoints onto a PCB layout
without putting a testpoint component on each net on my schematic?
Ideally I'd like to know the percent of nets covered by testpoints and
have someway to highlight or locate nets without a testpoint so I can
either add one or can decide that the particular net isn't worth the
trouble to test.
-Michael
"Michael Sansom" <mssansom@hotmail.com> wrote in message
news:ifb4bo$pg7$1@cheetah.cadsoft.de...
Is there a way to systematically insert ICT testpoints onto a PCB layout
without putting a testpoint component on each net on my schematic?
Ideally I'd like to know the percent of nets covered by testpoints and
have someway to highlight or locate nets without a testpoint so I can
either add one or can decide that the particular net isn't worth the
trouble to test.
-Michael
Hi Michael
Your requirements to reconcile net names with test pads and have a freely
placeable copper object in the layout editor would likely require a new
special object.
I imagine an object that is similar to the via, but un-drilled and only on
the top or bottom layer, would work to some degree.
What you are left with then is, like a via, only being able to determine if
one of these objects has a net name the same as a wire (routing). More code
is required to determine if they touch.
For now the following idea may be acceptable to you. Doing it this way you
will be able to get all the net name reporting you require, after a ULP is
written.
It does involve the schematic but visually there is only an increase in the
number of 'junction' dots displayed. I would expect that in most instances
you will use the junctions that are already drawn and occasionally have to
place one on a net wire.
The test points symbol is mostly on a new User layer which you only display
when needed.
The attached image shows what I mean.
Packages for these test points need placing in the layout editor but there
will be an airwire to assist.
Using Devices with multiple packages you can conveniently "Change Package"
in the board editor to lay down a differently sized test point that is more
appropriate for the available space.
If the test point needs to be away from a trace, this method lets you route
back to the trace as there is a valid net connected (airwire)
The 'Show' command displaying the complete net assists with choosing the
optimum place for the test point.
A ULP could now identify which nets do not attach to an element (your
various test point styles) with a nominated prefix.
One of the current assembly ULPs could provide the XY locations of the test
points and maybe their related net.
HTH
Warren
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end
"Michael Sansom" <mssansom@hotmail.com> wrote in message
news:ifb4bo$pg7$1@cheetah.cadsoft.de...
Is there a way to systematically insert ICT testpoints onto a PCB layout
without putting a testpoint component on each net on my schematic?
Ideally I'd like to know the percent of nets covered by testpoints and
have someway to highlight or locate nets without a testpoint so I can
either add one or can decide that the particular net isn't worth the
trouble to test.
-Michael
Hi Michael
Your requirements to reconcile net names with test pads and have a freely
placeable copper object in the layout editor would likely require a new
special object.
I imagine an object that is similar to the via, but un-drilled and only on
the top or bottom layer, would work to some degree.
What you are left with then is, like a via, only being able to determine if
one of these objects has a net name the same as a wire (routing). More code
is required to determine if they touch.
For now the following idea may be acceptable to you. Doing it this way you
will be able to get all the net name reporting you require, after a ULP is
written.
It does involve the schematic but visually there is only an increase in the
number of 'junction' dots displayed. I would expect that in most instances
you will use the junctions that are already drawn and occasionally have to
place one on a net wire.
The test points symbol is mostly on a new User layer which you only display
when needed.
The attached image shows what I mean.
Packages for these test points need placing in the layout editor but there
will be an airwire to assist.
Using Devices with multiple packages you can conveniently "Change Package"
in the board editor to lay down a differently sized test point that is more
appropriate for the available space.
If the test point needs to be away from a trace, this method lets you route
back to the trace as there is a valid net connected (airwire)
The 'Show' command displaying the complete net assists with choosing the
optimum place for the test point.
A ULP could now identify which nets do not attach to an element (your
various test point styles) with a nominated prefix.
One of the current assembly ULPs could provide the XY locations of the test
points and maybe their related net.
HTH
Warren
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end
On 12/28/2010 4:02 PM, Warren Brayshaw wrote:
"Michael Sansom"<mssansom@hotmail.com> wrote in message
news:ifb4bo$pg7$1@cheetah.cadsoft.de...
>> Is there a way to systematically insert ICT testpoints onto a PCB layout
>> without putting a testpoint component on each net on my schematic?
>> Ideally I'd like to know the percent of nets covered by testpoints and
>> have someway to highlight or locate nets without a testpoint so I can
>> either add one or can decide that the particular net isn't worth the
>> trouble to test.
>>
>> -Michael
Hi Michael
Your requirements to reconcile net names with test pads and have a freely
placeable copper object in the layout editor would likely require a new
special object.
I imagine an object that is similar to the via, but un-drilled and only on
the top or bottom layer, would work to some degree.
What you are left with then is, like a via, only being able to determine if
one of these objects has a net name the same as a wire (routing). More code
is required to determine if they touch.
For now the following idea may be acceptable to you. Doing it this way you
will be able to get all the net name reporting you require, after a ULP is
written.
It does involve the schematic but visually there is only an increase in the
number of 'junction' dots displayed. I would expect that in most instances
you will use the junctions that are already drawn and occasionally have to
place one on a net wire.
The test points symbol is mostly on a new User layer which you only display
when needed.
The attached image shows what I mean.
Packages for these test points need placing in the layout editor but there
will be an airwire to assist.
Using Devices with multiple packages you can conveniently "Change Package"
in the board editor to lay down a differently sized test point that is more
appropriate for the available space.
If the test point needs to be away from a trace, this method lets you route
back to the trace as there is a valid net connected (airwire)
The 'Show' command displaying the complete net assists with choosing the
optimum place for the test point.
A ULP could now identify which nets do not attach to an element (your
various test point styles) with a nominated prefix.
One of the current assembly ULPs could provide the XY locations of the test
points and maybe their related net.
HTH
Warren
Thanks for your suggestion Warren. That is certainly an improvement in
my opinion to the cluttered schematic that would result from attaching
visible test point components to the schematic on the majority of the nets.
Yes, I agree that a special component like a via would be required. In
fact, if I could just specify a via with no drill that would work as a
kludge.
Once again, thanks for the suggestion.
-Michael
Warren,
Thanks for your suggestion. It has proven to be the most workable near
term solution for placing ICT test points on schematics. I built a
schematic symbol much like you suggested. I used the point type symbol
pin, I assumed that you did the same. Putting it on a separate layer
really makes it workable. The only (small) fly in the ointment is the
connection dot that Eagle places when you drop the symbol on a net. As
you pointed out, it's completely invisible if you drop it on existing
connection dots and turn the test point layer off. I suppose that Eagle
is generating a short (or even null) wire segment and joining it to the
wire you dropped it on and generating the connection dot in the process.
Do you know of any way to modify this behavior of Eagle while still
getting the net connection to the test point?
Thanks again for the suggestion.
Regards,
-Michael
"Michael Sansom" wrote
Warren,
Thanks for your suggestion. It has proven to be the most workable near
term solution for placing ICT test points on schematics. I built a
schematic symbol much like you suggested. I used the point type symbol
pin, I assumed that you did the same. Putting it on a separate layer
really makes it workable. The only (small) fly in the ointment is the
connection dot that Eagle places when you drop the symbol on a net. As
you pointed out, it's completely invisible if you drop it on existing
connection dots and turn the test point layer off. I suppose that Eagle
is generating a short (or even null) wire segment and joining it to the
wire you dropped it on and generating the connection dot in the process.
Do you know of any way to modify this behavior of Eagle while still
getting the net connection to the test point?
Thanks again for the suggestion.
Regards,
-Michael
Hi Michael
Sounds as if you are doing it the way I suggested and don't have any ideas
to refine it any further. Since my initial response I have determined that
circles around the junction dots work best,in my opinion, (see attached).
You need to get the width of the circle wire to something you like.
Regards
Warren
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end
On 1/15/2011 6:20 PM, Warren Brayshaw wrote:
Hi Michael
Sounds as if you are doing it the way I suggested and don't have any ideas
to refine it any further. Since my initial response I have determined that
circles around the junction dots work best,in my opinion, (see attached).
You need to get the width of the circle wire to something you like.
Regards
Warren
Yes, I built my symbol with a circle as well. Think I used a 5 mil wire
width (0.127 mm) and it looked fairly decent.
I still say the best solution for this is for CadSoft to create a
testpoint object in the layout tool that, like you suggested, works like
a via without a drill. Then you could write a ULP to add unplaced
testpoints to the layout that the PCB designer could then place and
route. Your ULP might optionally load a list of net names that are to
have test points added (there are third party tools that will analyze a
netlist and generate a list of needed testpoints). If you wanted to get
really sophisticated your ULP could read your netlist and import the
BSDL files for whatever JTAG devices you have on the board and it would
skip placing testpoints for anything you can cover with a JTAG scan
chain. BSDL is just a subset of VHDL so it can be pretty readily
parsed. You'd probably also like the ability to attach a "no_test"
attribute on any nets that for instance, carried high speed signals
where a hanging testpoint might act as a stub and generate reflections
so the ULP would skip placing testpoints on those as well. This is all
sort of blue sky thinking but if Eagle would support such a testpoint
object you could do all sorts of cool things.
Someone mentioned the possibility of having a ULP autoplace the
testpoints and route them. Some might be interested in that, but
personally I'd be happy with just unplaced testpoints at the bottom of
the layout. I think a human can do a better job of looking at the trade
offs deciding the best place to drop the testpoint and route it.
Anyway, thanks for your help. This is now a part of my layout process.
-Michael
