Testpoints for ICT testers

"Michael Sansom" <mssansom@hotmail.com> wrote in message

news:ifb4bo$pg7$1@cheetah.cadsoft.de...

Is there a way to systematically insert ICT testpoints onto a PCB layout

without putting a testpoint component on each net on my schematic?

Ideally I'd like to know the percent of nets covered by testpoints and

have someway to highlight or locate nets without a testpoint so I can

either add one or can decide that the particular net isn't worth the

trouble to test.

 

-Michael

Hi Michael

Your requirements to reconcile net names with test pads and have a freely

placeable copper object in the layout editor would likely require a new

special object.

I imagine an object that is similar to the via, but un-drilled and only on

the top or bottom layer, would work to some degree.

What you are left with then is, like a via, only being able to determine if

one of these objects has a net name the same as a wire (routing). More code

is required to determine if they touch.

For now the following idea may be acceptable to you. Doing it this way you

will be able to get all the net name reporting you require, after a ULP is

written.

It does involve the schematic but visually there is only an increase in the

number of 'junction' dots displayed. I would expect that in most instances

you will use the junctions that are already drawn and occasionally  have to

place one on  a net wire.

The test points symbol is mostly on a new User layer which you only display

when needed.

The attached image shows what I mean.

Packages for these test points need placing in the layout editor but there

will be an airwire to assist.

Using Devices with multiple packages you can conveniently "Change Package"

in the board editor to lay down a differently sized test point that is more

appropriate for the available space.

If the test point needs to be away from a trace, this method lets you route

back to the trace as there is a valid net connected (airwire)

The 'Show' command displaying the complete net assists with choosing the

optimum place for the test point.

A ULP could now identify which nets do not attach to an element (your

various test point styles) with a nominated prefix.

One of the current assembly ULPs could provide the XY locations of the test

points and maybe their related net.

HTH

Warren

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end

On 12/28/2010 4:02 PM, Warren Brayshaw wrote:

"Michael Sansom"<mssansom@hotmail.com>  wrote in message

news:ifb4bo$pg7$1@cheetah.cadsoft.de...

>> Is there a way to systematically insert ICT testpoints onto a PCB layout

>> without putting a testpoint component on each net on my schematic?

>> Ideally I'd like to know the percent of nets covered by testpoints and

>> have someway to highlight or locate nets without a testpoint so I can

>> either add one or can decide that the particular net isn't worth the

>> trouble to test.

>>

>> -Michael

 

Hi Michael

 

Your requirements to reconcile net names with test pads and have a freely

placeable copper object in the layout editor would likely require a new

special object.

I imagine an object that is similar to the via, but un-drilled and only on

the top or bottom layer, would work to some degree.

What you are left with then is, like a via, only being able to determine if

one of these objects has a net name the same as a wire (routing). More code

is required to determine if they touch.

 

For now the following idea may be acceptable to you. Doing it this way you

will be able to get all the net name reporting you require, after a ULP is

written.

It does involve the schematic but visually there is only an increase in the

number of 'junction' dots displayed. I would expect that in most instances

you will use the junctions that are already drawn and occasionally  have to

place one on  a net wire.

The test points symbol is mostly on a new User layer which you only display

when needed.

The attached image shows what I mean.

Packages for these test points need placing in the layout editor but there

will be an airwire to assist.

Using Devices with multiple packages you can conveniently "Change Package"

in the board editor to lay down a differently sized test point that is more

appropriate for the available space.

If the test point needs to be away from a trace, this method lets you route

back to the trace as there is a valid net connected (airwire)

The 'Show' command displaying the complete net assists with choosing the

optimum place for the test point.

 

A ULP could now identify which nets do not attach to an element (your

various test point styles) with a nominated prefix.

One of the current assembly ULPs could provide the XY locations of the test

points and maybe their related net.

 

HTH

Warren

 

Thanks for your suggestion Warren.  That is certainly an improvement in

my opinion to the cluttered schematic that would result from attaching

visible test point components to the schematic on the majority of the nets.

Yes, I agree that a special component like a via would be required.  In

fact, if I could just specify a via with no drill that would work as a

kludge.

Once again, thanks for the suggestion.

-Michael

On 12/28/2010 4:02 PM, Warren Brayshaw wrote:

"Michael Sansom"<mssansom@hotmail.com>  wrote in message

news:ifb4bo$pg7$1@cheetah.cadsoft.de...

>> Is there a way to systematically insert ICT testpoints onto a PCB layout

>> without putting a testpoint component on each net on my schematic?

>> Ideally I'd like to know the percent of nets covered by testpoints and

>> have someway to highlight or locate nets without a testpoint so I can

>> either add one or can decide that the particular net isn't worth the

>> trouble to test.

>>

>> -Michael

 

Hi Michael

 

Your requirements to reconcile net names with test pads and have a freely

placeable copper object in the layout editor would likely require a new

special object.

I imagine an object that is similar to the via, but un-drilled and only on

the top or bottom layer, would work to some degree.

What you are left with then is, like a via, only being able to determine if

one of these objects has a net name the same as a wire (routing). More code

is required to determine if they touch.

 

For now the following idea may be acceptable to you. Doing it this way you

will be able to get all the net name reporting you require, after a ULP is

written.

It does involve the schematic but visually there is only an increase in the

number of 'junction' dots displayed. I would expect that in most instances

you will use the junctions that are already drawn and occasionally  have to

place one on  a net wire.

The test points symbol is mostly on a new User layer which you only display

when needed.

The attached image shows what I mean.

Packages for these test points need placing in the layout editor but there

will be an airwire to assist.

Using Devices with multiple packages you can conveniently "Change Package"

in the board editor to lay down a differently sized test point that is more

appropriate for the available space.

If the test point needs to be away from a trace, this method lets you route

back to the trace as there is a valid net connected (airwire)

The 'Show' command displaying the complete net assists with choosing the

optimum place for the test point.

 

A ULP could now identify which nets do not attach to an element (your

various test point styles) with a nominated prefix.

One of the current assembly ULPs could provide the XY locations of the test

points and maybe their related net.

 

HTH

Warren

 

Thanks for your suggestion Warren.  That is certainly an improvement in

my opinion to the cluttered schematic that would result from attaching

visible test point components to the schematic on the majority of the nets.

Yes, I agree that a special component like a via would be required.  In

fact, if I could just specify a via with no drill that would work as a

kludge.

Once again, thanks for the suggestion.

-Michael