Testpoints for ICT testers

Michael Sansom schrieb:

Is there a way to systematically insert ICT testpoints onto a PCB layout

without putting a testpoint component on each net on my schematic?

Not to my knowledege.

Ideally I'd like to know the percent of nets covered by testpoints and

have someway to highlight or locate nets without a testpoint so I can

either add one or can decide that the particular net isn't worth the

trouble to test.

You could write an ULP that collects all net names and then checks which

nets are connected to testpoints (which should be identifiable by a

common prefix, for example). The easiest way to provide the results is a

list containing covered and uncovered net names - and that would also be

sufficient for your decision.

I don't know if such an ULP already exists.

Tilmann

On 12/28/2010 2:12 AM, Tilmann Reh wrote:

Michael Sansom schrieb:

 

>> Is there a way to systematically insert ICT testpoints onto a PCB layout

>> without putting a testpoint component on each net on my schematic?

 

Not to my knowledege.

This is quite unfortunate.  In any engineering company I've ever

participated in of even a moderate size, the insertion of test points is

normally a post processing function, done by the PCB designer who more

often than not is not the engineer who generated the schematic.  The PCB

designer is generally tasked with inserting test points so as to insure

that a minimum fault coverage is achieved during ICT (say 90% perhaps).

  It is generally solely a function of the manufacturing/quality control

people to determine what test coverage level they desire and to insert

the test points to meet that level.  The design engineer generally

neither cares nor wants to be bothered with that information.  Only if

there are particular nets of interest that the design engineer wants to

ensure to be tested at ICT will he explicitly insert test points on the

schematic, and typically this will be for a very small percentage of the

total nets on the board.

Practically, having to insert all testpoints on the schematic results

in a cluttered, less readable schematic since you will in general want

to cover a high percentage of nets (ideally 100%).  If this is not a

planned feature for future versions of Eagle I would encourage CadSoft

to seriously consider it.

I would think you would accomplish this by having a special class of PCB

components which are specifically excluded from consideration when

doing a cross check between the PCB layout and the schematic netlist.

-Michael

On 12/28/2010 10:25 AM, Michael Sansom wrote:

On 12/28/2010 2:12 AM, Tilmann Reh wrote:

>> Michael Sansom schrieb:

>>

>>> Is there a way to systematically insert ICT testpoints onto a PCB layout

>>> without putting a testpoint component on each net on my schematic?

>>

>> Not to my knowledege.

After a few more minutes of consideration, I don't see why Eagle

couldn't treat testpoints exactly the way they currently treat plated

holes.  For instance, on the board I am currently working on, I have

four plated thru mounting hole.  These holes are electrically tied to a

net (GND), and yet they appear nowhere on my schematic.  They were added

during the PCB layout process and have nothing to do with the schematic.

  Like testpoints, they are single port elements, i.e. they make one and

only one connection to a single net, so they do not interfere with the

functionality established by the schematic.

Clearly, Eagle already has a mechanism for handling single port elements

that are added to the PCB manually but not to the schematic.  A

testpoint would simply be a similar element that consisted of a single

non-drilled pad.

On 12/29/2010 2:33 PM, Tilmann Reh wrote:

Michael Sansom schrieb:

 

>> Yes, agreed a via has a drill associated with it.  However, my point is

>> that Eagle already has a mechanism in place to for the PCB layout tool

>> to place a "single port" PCB component manually without causing any

>> consistency issues between the layout and the schematic.  We do it all

>> the time when we drop vias which of course are not represented on the

>> schematic (what a nightmare that would be!).

 

I think that for EAGLE, vias are /not/ a "single port" component, at

least not intentionally. Currently, vias are just a "vertical segment"

of a track.

Perhaps not.  But, from an electrical network point of view, they are

single port elements in that they connect to one and only one net.

However they may be implemented by Eagle internally, I still believe

that they would lend themselves to being made into test points without a

great deal of development.

>> Yes, we agree on what a ICTP is.  However, one would think that what

>> CadSoft already has in place to handle vias could be readily modified to

>> create an "add testpoint" button and command which would use perhaps 90%

>> of the code they have currently to handle vias.  A test point really is

>> just a one sided via with no drill.

 

I can't tell if it's really a simple modification/addition to the

existing code. Maybe it is - in that case I wouldn't mind if CadSoft

adds this function. (If it's more work, I wouldn't mind either - it's

just that I don't need ICTPs too often. )

Yes, the degree of difficulty is pure speculation on my part.  Only

CadSoft's developers know now hard or easy this task would be.

>>>> Do you really add test point components to all the nets on your schematic?

>>>

>>> Yes, if the customer wants me to (BTDT - not a big deal).

>>> No, otherwise, since we don't use ICT inhouse.

>>

>> That's probably the root of our difference of opinion on how test points

>> should be handled.  I have worked at several places where ICT testing

>> was emphasized, at one place for reliability/quality reasons, at others

>> for cost reduction reasons (i.e. to minimize the amount of hands-on

>> functional testing at the end of the manufacturing process.  At my small

>> company it is the latter reason driving my interest.

 

We already have done designs for customers that wanted/needed every net

on ICTPs for their production tests. As said, it's not a big deal even

if they are visible in the schematic. Maybe this is also related to the

complexity of a board - in our cases, they were not too big. Of course,

these testpoints have to be added in the schematic then, you can't

simply add them later in the board alone.

 

The cost structure for post-manufacturing test heavily depends on

production volumes - for our rather small quantities, automated ICT

equipment would never calculate. So obviously we are working on

different targets.

I'm looking at board that has a couple of small (thankfully) BGAs, a few

TSSOPS and SOICs and a couple of dozen discrete SMT components (I think

there's about 75 line items on my BOM) and would be made in 10k to 25k

piece monthly volumes (if the product succeeds that is).  The product is

relatively cost sensitive and the cost to build the ICT fixture is

easily amortized, even over the first 1,000 units built.

On 12/29/2010 2:33 PM, Tilmann Reh wrote:

Michael Sansom schrieb:

 

>> Yes, agreed a via has a drill associated with it.  However, my point is

>> that Eagle already has a mechanism in place to for the PCB layout tool

>> to place a "single port" PCB component manually without causing any

>> consistency issues between the layout and the schematic.  We do it all

>> the time when we drop vias which of course are not represented on the

>> schematic (what a nightmare that would be!).

 

I think that for EAGLE, vias are /not/ a "single port" component, at

least not intentionally. Currently, vias are just a "vertical segment"

of a track.

Perhaps not.  But, from an electrical network point of view, they are

single port elements in that they connect to one and only one net.

However they may be implemented by Eagle internally, I still believe

that they would lend themselves to being made into test points without a

great deal of development.

>> Yes, we agree on what a ICTP is.  However, one would think that what

>> CadSoft already has in place to handle vias could be readily modified to

>> create an "add testpoint" button and command which would use perhaps 90%

>> of the code they have currently to handle vias.  A test point really is

>> just a one sided via with no drill.

 

I can't tell if it's really a simple modification/addition to the

existing code. Maybe it is - in that case I wouldn't mind if CadSoft

adds this function. (If it's more work, I wouldn't mind either - it's

just that I don't need ICTPs too often. )

Yes, the degree of difficulty is pure speculation on my part.  Only

CadSoft's developers know now hard or easy this task would be.

>>>> Do you really add test point components to all the nets on your schematic?

>>>

>>> Yes, if the customer wants me to (BTDT - not a big deal).

>>> No, otherwise, since we don't use ICT inhouse.

>>

>> That's probably the root of our difference of opinion on how test points

>> should be handled.  I have worked at several places where ICT testing

>> was emphasized, at one place for reliability/quality reasons, at others

>> for cost reduction reasons (i.e. to minimize the amount of hands-on

>> functional testing at the end of the manufacturing process.  At my small

>> company it is the latter reason driving my interest.

 

We already have done designs for customers that wanted/needed every net

on ICTPs for their production tests. As said, it's not a big deal even

if they are visible in the schematic. Maybe this is also related to the

complexity of a board - in our cases, they were not too big. Of course,

these testpoints have to be added in the schematic then, you can't

simply add them later in the board alone.

 

The cost structure for post-manufacturing test heavily depends on

production volumes - for our rather small quantities, automated ICT

equipment would never calculate. So obviously we are working on

different targets.

I'm looking at board that has a couple of small (thankfully) BGAs, a few

TSSOPS and SOICs and a couple of dozen discrete SMT components (I think

there's about 75 line items on my BOM) and would be made in 10k to 25k

piece monthly volumes (if the product succeeds that is).  The product is

relatively cost sensitive and the cost to build the ICT fixture is

easily amortized, even over the first 1,000 units built.