Testpoints for ICT testers

Michael Sansom schrieb:

Is there a way to systematically insert ICT testpoints onto a PCB layout

without putting a testpoint component on each net on my schematic?

Not to my knowledege.

Ideally I'd like to know the percent of nets covered by testpoints and

have someway to highlight or locate nets without a testpoint so I can

either add one or can decide that the particular net isn't worth the

trouble to test.

You could write an ULP that collects all net names and then checks which

nets are connected to testpoints (which should be identifiable by a

common prefix, for example). The easiest way to provide the results is a

list containing covered and uncovered net names - and that would also be

sufficient for your decision.

I don't know if such an ULP already exists.

Tilmann

On 12/28/2010 2:12 AM, Tilmann Reh wrote:

Michael Sansom schrieb:

 

>> Is there a way to systematically insert ICT testpoints onto a PCB layout

>> without putting a testpoint component on each net on my schematic?

 

Not to my knowledege.

This is quite unfortunate.  In any engineering company I've ever

participated in of even a moderate size, the insertion of test points is

normally a post processing function, done by the PCB designer who more

often than not is not the engineer who generated the schematic.  The PCB

designer is generally tasked with inserting test points so as to insure

that a minimum fault coverage is achieved during ICT (say 90% perhaps).

  It is generally solely a function of the manufacturing/quality control

people to determine what test coverage level they desire and to insert

the test points to meet that level.  The design engineer generally

neither cares nor wants to be bothered with that information.  Only if

there are particular nets of interest that the design engineer wants to

ensure to be tested at ICT will he explicitly insert test points on the

schematic, and typically this will be for a very small percentage of the

total nets on the board.

Practically, having to insert all testpoints on the schematic results

in a cluttered, less readable schematic since you will in general want

to cover a high percentage of nets (ideally 100%).  If this is not a

planned feature for future versions of Eagle I would encourage CadSoft

to seriously consider it.

I would think you would accomplish this by having a special class of PCB

components which are specifically excluded from consideration when

doing a cross check between the PCB layout and the schematic netlist.

-Michael

Michael Sansom wrote on Tue, 28 December 2010 11:25

In any engineering company I've ever

participated in of even a moderate size, the insertion of test points

is

normally a post processing function, done by the PCB designer who more

 

often than not is not the engineer who generated the schematic.

That's a bad idea.  If you have a separate person doing the layout (that

itself is usually not a good idea), then they are usually a draftsman and

not a electrical engineer.  They can't look at the circuit and determine

which nets need to be brought out to be measured or driven externally

during board test.  This process may include a separate production test

engineer, but should always include the circuit designer.

For example, many points connected to a microcontroller don't need to be

connected directly to the tester.  Usually you set up a communication link

to the microcontroller and have it report on the state of signals or drive

them as required.  With a little cleverness, you can infer the operation of

components between the external connections and the micro too sometimes.

The point is, you don't want to blindly connect a pogo pin pad (or whatever

you use to connect to the tester) to every net.  That would add needless

complexity to the board, the tester, and the test process.

Since you have to think about where to connect test points, these should be

on the schematic.  Someone will need to review the test plan, which will

include matching test point on the board with the schematic.  For

troubleshooting you want to know what TP7, for example, is connected to.

Or often you have the reverse case where you want to put a scope probe on a

particular net and want to know if it has a test point, where it is on the

board, and how it's labeled.  In other words, you want test points to show

up in the cross reference list just like any other component.

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

On 12/30/2010 8:08 AM, Olin Lathrop wrote:

Wow, that was a amazing bit of sideways logic. I was reacting to your

rediculous assertion that you always need to give a tester access to all

nets. It only takes a single counter example to disprove that, and I

supplied several such counter examples.

 

Your response is to act as if I said you are always limited to doing things

as in the counter examples, which is completely illogical.

 

Of course there are many methods to test a board. The point is that you

don't always need to have access to every net, not that you should never

have access to any net.

Sorry, been traveling for some time, back in the office now.

If I used sideways logic then you are just as guilty of it.  I gave you

several counter examples where your methodology would not work and

several points on how your way can in some cases cause you to spend

recurring costs on the BOM, yet you choose to ignore those as well.  So,

perhaps we are both guilty of sideways logic.

I have never claimed that I want access to every net on a board in all

cases.  Sometimes I might (particularly if it's a board with no

microcontroller or reprogrammable logic, which I certainly admit is

rather rare).  In fact, in general I want to use a combination of

methodologies to do automated testing of boards.  Ideally, I'd use JTAG,

ICT test points, and yes your method as well where appropriate

(meaning where possible and where it does not incur recurring BOM cost).

  A mix of methods will give me the most thorough and cost effective

means to test a populated board.

In summary I still propose that CadSoft should consider a means to add

test points during layout without adding them explicitly to the

schematic, (much like the way we add vias).  This is supported in many

of the major CAD systems that Eagle competes with and follows the

methodology and division of labor used by many enterprises.

On 12/30/2010 8:08 AM, Olin Lathrop wrote:

Wow, that was a amazing bit of sideways logic. I was reacting to your

rediculous assertion that you always need to give a tester access to all

nets. It only takes a single counter example to disprove that, and I

supplied several such counter examples.

 

Your response is to act as if I said you are always limited to doing things

as in the counter examples, which is completely illogical.

 

Of course there are many methods to test a board. The point is that you

don't always need to have access to every net, not that you should never

have access to any net.

Sorry, been traveling for some time, back in the office now.

If I used sideways logic then you are just as guilty of it.  I gave you

several counter examples where your methodology would not work and

several points on how your way can in some cases cause you to spend

recurring costs on the BOM, yet you choose to ignore those as well.  So,

perhaps we are both guilty of sideways logic.

I have never claimed that I want access to every net on a board in all

cases.  Sometimes I might (particularly if it's a board with no

microcontroller or reprogrammable logic, which I certainly admit is

rather rare).  In fact, in general I want to use a combination of

methodologies to do automated testing of boards.  Ideally, I'd use JTAG,

ICT test points, and yes your method as well where appropriate

(meaning where possible and where it does not incur recurring BOM cost).

  A mix of methods will give me the most thorough and cost effective

means to test a populated board.

In summary I still propose that CadSoft should consider a means to add

test points during layout without adding them explicitly to the

schematic, (much like the way we add vias).  This is supported in many

of the major CAD systems that Eagle competes with and follows the

methodology and division of labor used by many enterprises.