Overlapping Pads

Tim Wescott wrote:

I have two problems that I need to solve, both involving high-current

circuits:

 

First, I'm going to be laying down some FETs in SO-8 packages, and I

want a good solid connection from the four drain pins to a surrounding

polygon, both for current flow and to provide a thermal path for heat

sinking.  For the same part I want the same solid connection to the

source pins, although I don't need a polygon.  Connections that allow

good wide traces (up to 200 mils would be nice) without stomping on

the gate connection would be nice.

 

Second, I'll be putting in some current sense resistors.  While I'm

going cheap and using 2-terminal resistors, I'd like to make a pseudo

4- terminal device by laying the part out with four pads, but then

connecting pairs of pads with a polygon or some such so that it looks

and solders like a regular resistor, but so that I can have my nice

high- current connections going to it with honkin' big traces, and

still have some thin traces coming off of the pads -- independent of

the big traces -- in a "pseudo Kelvin" connection.

 

Has anyone solved this problem before?  Got any suggestions on how to

proceed?

Hi Tim

Mock up an image of what you are attempting. That would make a potentially

long reply more targetted.

Warren

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Tim

See this document

http://www.irf.com/technical-info/appnotes/an-1154.pdf

Do you want to achieve the land pattens they have for their SO8

Fig 4

Warren

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Tim

See this document

http://www.irf.com/technical-info/appnotes/an-1154.pdf

Do you want to achieve the land pattens they have for their SO8

Fig 4

Warren

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Tim Wescott wrote:

On Tue, 07 Feb 2012 07:56:59 +1300, Warren Brayshaw wrote:

 

>> Tim Wescott wrote:

>>> I have two problems that I need to solve, both involving

>>> high-current circuits:

>>>

>>> First, I'm going to be laying down some FETs in SO-8 packages, and I

>>> want a good solid connection from the four drain pins to a

>>> surrounding polygon, both for current flow and to provide a thermal

>>> path for heat sinking.  For the same part I want the same solid

>>> connection to the source pins, although I don't need a polygon.

>>> Connections that allow good wide traces (up to 200 mils would be

>>> nice) without stomping on the gate connection would be nice.

>>>

As you know that 4 pins on one side are common and three on the other are

common I would make a library device that a single pad covering those

regions, including the heat sink.

That gives only 3 pins of the symbol to match with three pads of the

package. When placed on the board, connect up with modest traces initially .

Then plonk a polygon over the drain and source pins as required to get the

copper coverage.

Name these polygons to match the signal name at the drain and source as

appropriate.

Increase the sizes of the feeder traces as best you can.

HTH

Warren

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