High Current Traces

OK, final post on this.  After a bunch of tweaks, I've gotten everything to route with this last problem.

I have a QFN24 package that has 6 output pins which together provide up to 5 amps.  Each pin has a width of 0.25 mm.  The 6 pins are overlaid with a polygon which is connected to one of my high current traces.  My high current trace is 0.5 mm.  The router creates traces which are the width of the wide netclass trace, 0.5 mm, and even though there is a polygon connecting the pins, the router runs traces between all the pins.

Here's the problem.  At the end points of the polygon connecting the 6 pins, the 0.5 mm traces extend past the 0.25 mm pads, violating the spacing to the next pins.  I can't change the width of the pins or the width of the traces.  Do I rip just those traces then route manually?

Thanks,

Dave

OK, final post on this.  After a bunch of tweaks, I've gotten everything to route with this last problem.

I have a QFN24 package that has 6 output pins which together provide up to 5 amps.  Each pin has a width of 0.25 mm.  The 6 pins are overlaid with a polygon which is connected to one of my high current traces.  My high current trace is 0.5 mm.  The router creates traces which are the width of the wide netclass trace, 0.5 mm, and even though there is a polygon connecting the pins, the router runs traces between all the pins.

Here's the problem.  At the end points of the polygon connecting the 6 pins, the 0.5 mm traces extend past the 0.25 mm pads, violating the spacing to the next pins.  I can't change the width of the pins or the width of the traces.  Do I rip just those traces then route manually?

Thanks,

Dave

Hi Dave,

For easier visualisation, a screenshot of this problematic PCB part would be useful... ;-)

Anyway, I can read your fear about high currents and traces width. That's ok, but current is not the only parameter to be considered during traces width selection. Actually, it is the temperature which you should have in mind. When you have good air flow or larger enclosure, you can decrease traces width.

To avoid guessing, you can use one of online calculators which return min trace width based on your temperatures (environment and max allowed trace temperature) and few laminate properties. Hopefully, you will find out that 0.25mm is enough.

Best wishes,  Ivan.

Ivan Zilic wrote:

 

Hi Dave,

 

For easier visualisation, a screenshot of this problematic PCB part would be useful... ;-)

 

Anyway, I can read your fear about high currents and traces width. That's ok, but current is not the only parameter to be considered during traces width selection. Actually, it is the temperature which you should have in mind. When you have good air flow or larger enclosure, you can decrease traces width.

To avoid guessing, you can use one of online calculators which return min trace width based on your temperatures (environment and max allowed trace temperature) and few laminate properties. Hopefully, you will find out that 0.25mm is enough.

 

 

Best wishes,  Ivan.

Hi Ivan,

Yes, I've considered trace temperature and I think I'm being conservative regarding trace width.  I'd rather err on the safe side and I think I'm pretty close to routing with 0.50 mm traces on the high current lines, including the low current traces on the same net as the high current traces.

But I still have this one clearance issue when the 0.25 mm pad is routed with a 0.50 mm trace.  A picture of this is below.  Two pins on the top right (pins 16 & 15) and four pins coming down the right side from the top (pins 14 through 11) are on the same net.  You can see the bulge on pin 16 which is too close to pin 17, and a similar bulge between pins 11 and 10.  These bulges are the 0.50 mm traces added by the router.  I can rip those traces, but even if I route manually they are the same 0.50 mm width and I have the same problem.  There is also a polygon with the same net sitting on top of these pads and extending to the right.  (Some caps sit on the other end of the polygon.)

I tried eliminating 5 of the pins in the symbol, then putting a polygon in the package to cover the 1 remaining pin and where the other 5 pins would be.  But that gives me an overlap error.

I'll keep trying things but if anyone has a good idea, let me know.

Thanks,

Dave

Hi Dave,

Ok, I see now. :-)

There are two possible solutions. The first would be to "partially" decrease traces width just between pins 15 & 16 (and 11 & 12). You can do this trick by routing three traces instead of one between those pins and editing each trace section - middle section is 0.5mm, remaining two are thinner and are present just to avoid errors.

The second approach is to place a polygon (and name it with net's name, additionally uncheck Thermals option).

Please find attached example screenshot of the description above.

At the picture top you can see just traces/polygon, at the bottom these traces/polygon are presented with chip pins.

From left to right, first is your approach, then 3-traces solution (the two error-avoiding traces are highlighted in orange, just to point out that they are present) and the most right is a polygon.

Probably there are also some other solutions, but I'm not aware of any which would not require some manual intervention.

Best wishes,  Ivan.

Hmmm...  Maybe I'm being too obsessed with eliminating the errors/warnings.  Why couldn't I just rip those couple of traces, get rid of the polygons (which have line width) and draw a rectangle on that layer of the board overlapping the pins (to replace the polygon).  That would give me overlap errors, but so what?  As long as the rectangle (or overlapping rectangles) connects the pins, it should be OK.

Is this a simple solution?  (I don't want to go for fab then find out I missed something.  )

Dave

I think I've fixed it.  What I did was to let the auto router route the wires, then change the wire width to something really small.  This reduces the extension of the formerly 0.50 mm wire outside of the pin to something really small.  And since the 0.25 mm pin is overlaid with a polygon, that shouldn't be a problem.  I do get width errors, but I think these are OK because of the polygon.

But in order to prevent the polygon from encroaching on the next pin, I've made the polygon width really small (0.01 mm).  That gives me width errors too.

Since the polygon is filled, the width errors should be OK, right?

Thanks to all for the help.

Dave

Sorry, I just keep running into roadblocks on this.  There are 2 pictures of my board below, one after routing and one before routing.  The numbered squares are the pin numbers for the IC, 9 through 19 (10 left out).

Pin 9 is on a wider net class (0.38 mm) than default  0.10 mm.  The pin width is only 0.25 mm and so pin 9 can't be routed automatically.  But since pin 9 is not a high current signal, I can route it manually with a 0.25 mm trace and that works fine.  The trace is shown as E in the top picture.  It goes up, then left to pad A.

A and C are pads of capacitors and D is the pad of an inductor.  B is all that is left of the polygon I inserted.  If you look at the bottom picture you see the polygon extends all the way from A to D, and is 0.38 mm wide so I don't get a width violation.  Even so, when adding in the width of the polygon all is contained within the area I want to cover.  The polygon is solid, but it looks like the router trimmed it down.  I don't want it trimmed down.

F and H are parts of the next polygon below.  The pins and polygon are on a net class of 0.50 mm.  This polygon covers pins 11 through 16, around the corner of the IC and inductor pad G.  Again, you can see the polygon unrouted in the bottom picture.  There are 2 bad things about this.  First, even though I've positioned the polygon so it does not extend outside of the pins (bottom picture), the router added wires between pins 11 and 12, and 15 and 16.  These are the bulges I mentioned in previous posts and you can see the clearance warnings.  I think I can get rid of these by changing the wire size after routing, as long as the polygon covers the pins.  Next, the router trimmed my polygon which extended from pad G all the way to the bottom of pin 16.  And even though F, G and H are all within the polygon, as is the via next to H, the router says the connection to pad G is not routed.  ???

The polygon from pins 17, 18 and 19 has similar issues.  The polygon has been trimmed.  The net class here is 0.38 mm, but it's still weird that when the router connected pins 17 and 18 that it didn't bulge towards pin 16.  Same with pin 19.  (Again, the pins are 0.25 mm wide.)

So those are the details.  Questions are included above, but for simplicity:

- Why are the polygons trimmed?

- I can change wire size to prevent the bulges on the pins, but that works only if the polygons are not trimmed.  How do I fix this?

- Why is the one trace unrouted even though the 6 pins, the inductor pad, the polygon and the via all have the same name?

Thanks for taking a look.

Dave

On 6/14/2012 3:03 PM, Dave Wills wrote:

Sorry, I just keep running into roadblocks on this.  There are 2 pictures of my board below, one after routing and one before routing.  The numbered squares are the pin numbers for the IC, 9 through 19 (10 left out).

 

Pin 9 is on a wider net class (0.38 mm) than default  0.10 mm.  The pin width is only 0.25 mm and so pin 9 can't be routed automatically.  But since pin 9 is not a high current signal, I can routed it manually with a 0.25 mm trace and that works fine.  The trace is shown as E in the top picture.  It goes up, then left to pad A.

 

A and C are pads of capacitors and D is the pad of an inductor.  B is all that is left of the polygon I inserted.  If you look at the bottom picture you see the polygon extends all the way from A to D, and is 0.38 mm wide so I don't get a width violation.  Even so, when adding in the width of the polygon all is contained within the area I want to cover.  The polygon is solid, but it looks like the router trimmed it down.  I don't want it trimmed down.

 

F and H are parts of the next polygon below.  The pins and polygon are on a net class of 0.50 mm.  This polygon covers pins 11 through 16, around the corner of the IC and inductor pad G.  Again, you can see the polygon unrouted in the bottom picture.  There are 2 bad things about this.  First, even though I've positioned the polygon so it does not extend outside of the pins (bottom picture), the router added wires between pins 11 and 12, and 15 and 16.  These are the bulges I mentioned in previous posts and you can see the clearance warnings.  I think I can get rid of these by changing the wire size after routing, as long as the polygon covers the pins.  Next, the router trimmed my polygon which extended from pad G all the way to the bottom of pin 16.  And even though F, G and H are all within the polygon, as is the via next to H, the router says the connection to pad G is not routed.  ???

 

The polygon from pins 17, 18 and 19 has similar issues.  The polygon has been trimmed.  The net class here is 0.38 mm, but it's still weird that when the router connected pins 17 and 18 that it didn't bulge towards pin 16.  Same with pin 19.  (Again, the pins are 0.25 mm wide.)

 

So those are the details.  Questions are included above, but for simplicity:

 

- Why are the polygons trimmed?

 

- I can change wire size to prevent the bulges on the pins, but that works only if the polygons are not trimmed.  How do I fix this?

 

- Why is the one trace unrouted even though the 6 pins, the inductor pad, the polygon and the via all have the same name?

 

Thanks for taking a look.

 

Dave

 

  Image:board.png

 

Your pictures did not make it to the newgroup or to eaglecentral.ca

Jim

Guest wrote:

 

On 6/14/2012 3:03 PM, Dave Wills wrote:

Sorry, I just keep running into roadblocks on this.  There are 2 pictures of my board below, one after routing and one before routing.  The numbered squares are the pin numbers for the IC, 9 through 19 (10 left out).

 

Pin 9 is on a wider net class (0.38 mm) than default  0.10 mm.  The pin width is only 0.25 mm and so pin 9 can't be routed automatically.  But since pin 9 is not a high current signal, I can routed it manually with a 0.25 mm trace and that works fine.  The trace is shown as E in the top picture.  It goes up, then left to pad A.

 

A and C are pads of capacitors and D is the pad of an inductor.  B is all that is left of the polygon I inserted.  If you look at the bottom picture you see the polygon extends all the way from A to D, and is 0.38 mm wide so I don't get a width violation.  Even so, when adding in the width of the polygon all is contained within the area I want to cover.  The polygon is solid, but it looks like the router trimmed it down.  I don't want it trimmed down.

 

F and H are parts of the next polygon below.  The pins and polygon are on a net class of 0.50 mm.  This polygon covers pins 11 through 16, around the corner of the IC and inductor pad G.  Again, you can see the polygon unrouted in the bottom picture.  There are 2 bad things about this.  First, even though I've positioned the polygon so it does not extend outside of the pins (bottom picture), the router added wires between pins 11 and 12, and 15 and 16.  These are the bulges I mentioned in previous posts and you can see the clearance warnings.  I think I can get rid of these by changing the wire size after routing, as long as the polygon covers the pins.  Next, the router trimmed my polygon which extended from pad G all the way to the bottom of pin 16.  And even though F, G and H are all within the polygon, as is the via next to H, the router says the connection to pad G is not routed.  ???

 

The polygon from pins 17, 18 and 19 has similar issues.  The polygon has been trimmed.  The net class here is 0.38 mm, but it's still weird that when the router connected pins 17 and 18 that it didn't bulge towards pin 16.  Same with pin 19.  (Again, the pins are 0.25 mm wide.)

 

So those are the details.  Questions are included above, but for simplicity:

 

- Why are the polygons trimmed?

 

- I can change wire size to prevent the bulges on the pins, but that works only if the polygons are not trimmed.  How do I fix this?

 

- Why is the one trace unrouted even though the 6 pins, the inductor pad, the polygon and the via all have the same name?

 

Thanks for taking a look.

 

Dave

 

  Image:board.png

 

 

Your pictures did not make it to the newgroup or to eaglecentral.ca

 

Jim

 

 

Hmmm...  I see it just fine in the post.  Maybe you're having problem with the .png.  Here's a .jpg.

Thanks,

Dave

Dave Wills wrote:

Guest wrote:

>

> On 6/14/2012 3:03 PM, Dave Wills wrote:

>> Sorry, I just keep running into roadblocks on this. There are 2

>> pictures of my board below, one after routing and one before

>> routing. The numbered squares are the pin numbers for the IC, 9

>> through 19 (10 left out).

>>

>> Pin 9 is on a wider net class (0.38 mm) than default 0.10 mm. The

>> pin width is only 0.25 mm and so pin 9 can't be routed

>> automatically. But since pin 9 is not a high current signal, I can

>> routed it manually with a 0.25 mm trace and that works fine. The

>> trace is shown as E in the top picture. It goes up, then left to pad

>> A.

>>

>> A and C are pads of capacitors and D is the pad of an inductor. B is

>> all that is left of the polygon I inserted. If you look at the

>> bottom picture you see the polygon extends all the way from A to D,

>> and is 0.38 mm wide so I don't get a width violation. Even so, when

>> adding in the width of the polygon all is contained within the area

>> I want to cover. The polygon is solid, but it looks like the router

>> trimmed it down. I don't want it trimmed down.

>>

>> F and H are parts of the next polygon below. The pins and polygon

>> are on a net class of 0.50 mm. This polygon covers pins 11 through

>> 16, around the corner of the IC and inductor pad G. Again, you can

>> see the polygon unrouted in the bottom picture. There are 2 bad

>> things about this. First, even though I've positioned the polygon so

>> it does not extend outside of the pins (bottom picture), the router

>> added wires between pins 11 and 12, and 15 and 16. These are the

>> bulges I mentioned in previous posts and you can see the clearance

>> warnings. I think I can get rid of these by changing the wire size

>> after routing, as long as the polygon covers the pins. Next, the

>> router trimmed my polygon which extended from pad G all the way to

>> the bottom of pin 16. And even though F, G and H are all within the

>> polygon, as is the via next to H, the router says the connection to

>> pad G is not routed. ???

>>

>> The polygon from pins 17, 18 and 19 has similar issues. The polygon

>> has been trimmed. The net class here is 0.38 mm, but it's still

>> weird that when the router connected pins 17 and 18 that it didn't

>> bulge towards pin 16. Same with pin 19. (Again, the pins are 0.25 mm

>> wide.)

>>

>> So those are the details. Questions are included above, but for

>> simplicity:

>>

>> - Why are the polygons trimmed?

>>

>> - I can change wire size to prevent the bulges on the pins, but that

>> works only if the polygons are not trimmed. How do I fix this?

>>

>> - Why is the one trace unrouted even though the 6 pins, the inductor

>> pad, the polygon and the via all have the same name?

>>

>> Thanks for taking a look.

>>

>> Dave

>>

>> Image:board.png

>>

>

> Your pictures did not make it to the newgroup or to eaglecentral.ca

>

> Jim

>

>

Hmmm... I see it just fine in the post. Maybe you're having problem

with the .png. Here's a .jpg.

 

Thanks,

 

Dave

 

Image:board.jpg

No Dave

The problem is you are using the Element14 site and that has always been

broken. Images don't get through. Attachments can get through but only if

you  do them a particular way.

It's a "Johnny come lately" that was not implemented well.

If you prefer a web access to the to the support forums it is recommended

you use eaglecentral

http://www.eaglecentral.ca/forums/

Only downside there is getting approved , but that's only a day. Searching

for old posts is great there.

Both these web portals are front ends to the master newsgroup forum

repository at

new.cadsoft.de

Get a newsreader set up, it's just like dealing with emails

HTH

Warren

--

Viewed / responded via the newsgroup at

news.cadsoft.de

Registered, but still cannot post a day later.

d.