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Autodesk EAGLE
EAGLE User Support (English) High Current Traces
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  • current
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High Current Traces

e14 Contributor
e14 Contributor over 14 years ago

Hi,

 

I'm a new Eagle user, but I suspect this is actually a more complicated question.

 

I have traces that will carry up to 2 amps.  Those traces also control various FETs and other signals.  If I set that net node to the trace width for the high current, all of the net gets set to that width and I don't have room to route my board.  I've already re-arranged all my components so that the wide traces are short and the pins near each other.  I've even gone from 4 layers to 6 layers.  (The board routes just fine with 4 layers by 7 mil traces.)

 

I don't see a way to set the width of signals before routing, and after routing is too late.  One idea is to isolate the low current part of the net from the high current with a 0 ohm resistor, then after routing fill in will a trace.  But even that seems a little clumsy.

 

I'm considering going to thicker copper layers so that I can reduce the trace width, but I haven't tried that yet.

 

Does anyone have any ideas on how I might solve this problem?

 

Thanks,

 

Dave

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  • e14 Contributor
    e14 Contributor over 14 years ago

    OK, final post on this.  After a bunch of tweaks, I've gotten everything to route with this last problem.

     

    I have a QFN24 package that has 6 output pins which together provide up to 5 amps.  Each pin has a width of 0.25 mm.  The 6 pins are overlaid with a polygon which is connected to one of my high current traces.  My high current trace is 0.5 mm.  The router creates traces which are the width of the wide netclass trace, 0.5 mm, and even though there is a polygon connecting the pins, the router runs traces between all the pins.

     

    Here's the problem.  At the end points of the polygon connecting the 6 pins, the 0.5 mm traces extend past the 0.25 mm pads, violating the spacing to the next pins.  I can't change the width of the pins or the width of the traces.  Do I rip just those traces then route manually?

     

    Thanks,

     

    Dave

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  • e14 Contributor
    e14 Contributor over 14 years ago in reply to e14 Contributor

    Hi Dave,

     

    For easier visualisation, a screenshot of this problematic PCB part would be useful... ;-)

     

    Anyway, I can read your fear about high currents and traces width. That's ok, but current is not the only parameter to be considered during traces width selection. Actually, it is the temperature which you should have in mind. When you have good air flow or larger enclosure, you can decrease traces width.

    To avoid guessing, you can use one of online calculators which return min trace width based on your temperatures (environment and max allowed trace temperature) and few laminate properties. Hopefully, you will find out that 0.25mm is enough.

     

     

    Best wishes,  Ivan.

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  • e14 Contributor
    e14 Contributor over 14 years ago in reply to e14 Contributor

    Ivan Zilic wrote:

     

    Hi Dave,

     

    For easier visualisation, a screenshot of this problematic PCB part would be useful... ;-)

     

    Anyway, I can read your fear about high currents and traces width. That's ok, but current is not the only parameter to be considered during traces width selection. Actually, it is the temperature which you should have in mind. When you have good air flow or larger enclosure, you can decrease traces width.

    To avoid guessing, you can use one of online calculators which return min trace width based on your temperatures (environment and max allowed trace temperature) and few laminate properties. Hopefully, you will find out that 0.25mm is enough.

     

     

    Best wishes,  Ivan.

    Hi Ivan,

     

    Yes, I've considered trace temperature and I think I'm being conservative regarding trace width.  I'd rather err on the safe side and I think I'm pretty close to routing with 0.50 mm traces on the high current lines, including the low current traces on the same net as the high current traces.

     

    But I still have this one clearance issue when the 0.25 mm pad is routed with a 0.50 mm trace.  A picture of this is below.  Two pins on the top right (pins 16 & 15) and four pins coming down the right side from the top (pins 14 through 11) are on the same net.  You can see the bulge on pin 16 which is too close to pin 17, and a similar bulge between pins 11 and 10.  These bulges are the 0.50 mm traces added by the router.  I can rip those traces, but even if I route manually they are the same 0.50 mm width and I have the same problem.  There is also a polygon with the same net sitting on top of these pads and extending to the right.  (Some caps sit on the other end of the polygon.)

     

    I tried eliminating 5 of the pins in the symbol, then putting a polygon in the package to cover the 1 remaining pin and where the other 5 pins would be.  But that gives me an overlap error.

     

    I'll keep trying things but if anyone has a good idea, let me know.

     

    Thanks,

     

    Dave

    image

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  • e14 Contributor
    e14 Contributor over 14 years ago in reply to e14 Contributor

    Registered, but still cannot post a day later.

     

    d.

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  • e14 Contributor
    e14 Contributor over 14 years ago in reply to e14 Contributor

    Registered, but still cannot post a day later.

     

    d.

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