High Current Traces

Hmmm...  Maybe I'm being too obsessed with eliminating the errors/warnings.  Why couldn't I just rip those couple of traces, get rid of the polygons (which have line width) and draw a rectangle on that layer of the board overlapping the pins (to replace the polygon).  That would give me overlap errors, but so what?  As long as the rectangle (or overlapping rectangles) connects the pins, it should be OK.

Is this a simple solution?  (I don't want to go for fab then find out I missed something.  )

Dave

Hi Dave,

Ok, I see now. :-)

There are two possible solutions. The first would be to "partially" decrease traces width just between pins 15 & 16 (and 11 & 12). You can do this trick by routing three traces instead of one between those pins and editing each trace section - middle section is 0.5mm, remaining two are thinner and are present just to avoid errors.

The second approach is to place a polygon (and name it with net's name, additionally uncheck Thermals option).

Please find attached example screenshot of the description above.

At the picture top you can see just traces/polygon, at the bottom these traces/polygon are presented with chip pins.

From left to right, first is your approach, then 3-traces solution (the two error-avoiding traces are highlighted in orange, just to point out that they are present) and the most right is a polygon.

Probably there are also some other solutions, but I'm not aware of any which would not require some manual intervention.

Best wishes,  Ivan.

Ivan Zilic wrote:

 

Hi Dave,

 

For easier visualisation, a screenshot of this problematic PCB part would be useful... ;-)

 

Anyway, I can read your fear about high currents and traces width. That's ok, but current is not the only parameter to be considered during traces width selection. Actually, it is the temperature which you should have in mind. When you have good air flow or larger enclosure, you can decrease traces width.

To avoid guessing, you can use one of online calculators which return min trace width based on your temperatures (environment and max allowed trace temperature) and few laminate properties. Hopefully, you will find out that 0.25mm is enough.

 

 

Best wishes,  Ivan.

Hi Ivan,

Yes, I've considered trace temperature and I think I'm being conservative regarding trace width.  I'd rather err on the safe side and I think I'm pretty close to routing with 0.50 mm traces on the high current lines, including the low current traces on the same net as the high current traces.

But I still have this one clearance issue when the 0.25 mm pad is routed with a 0.50 mm trace.  A picture of this is below.  Two pins on the top right (pins 16 & 15) and four pins coming down the right side from the top (pins 14 through 11) are on the same net.  You can see the bulge on pin 16 which is too close to pin 17, and a similar bulge between pins 11 and 10.  These bulges are the 0.50 mm traces added by the router.  I can rip those traces, but even if I route manually they are the same 0.50 mm width and I have the same problem.  There is also a polygon with the same net sitting on top of these pads and extending to the right.  (Some caps sit on the other end of the polygon.)

I tried eliminating 5 of the pins in the symbol, then putting a polygon in the package to cover the 1 remaining pin and where the other 5 pins would be.  But that gives me an overlap error.

I'll keep trying things but if anyone has a good idea, let me know.

Thanks,

Dave

Hi Dave,

For easier visualisation, a screenshot of this problematic PCB part would be useful... ;-)

Anyway, I can read your fear about high currents and traces width. That's ok, but current is not the only parameter to be considered during traces width selection. Actually, it is the temperature which you should have in mind. When you have good air flow or larger enclosure, you can decrease traces width.

To avoid guessing, you can use one of online calculators which return min trace width based on your temperatures (environment and max allowed trace temperature) and few laminate properties. Hopefully, you will find out that 0.25mm is enough.

Best wishes,  Ivan.

OK, final post on this.  After a bunch of tweaks, I've gotten everything to route with this last problem.

I have a QFN24 package that has 6 output pins which together provide up to 5 amps.  Each pin has a width of 0.25 mm.  The 6 pins are overlaid with a polygon which is connected to one of my high current traces.  My high current trace is 0.5 mm.  The router creates traces which are the width of the wide netclass trace, 0.5 mm, and even though there is a polygon connecting the pins, the router runs traces between all the pins.

Here's the problem.  At the end points of the polygon connecting the 6 pins, the 0.5 mm traces extend past the 0.25 mm pads, violating the spacing to the next pins.  I can't change the width of the pins or the width of the traces.  Do I rip just those traces then route manually?

Thanks,

Dave

Hi Ivan,

Thanks for the suggestions.  Yes, that's pretty much what I thought

needed to be done.  But as my initial report said, I'm a new user so

I'm still learning a lot.  One thing that stops me from manually

routing is I ran into a roadblock adding vias.  I couldn't figure out

how to make the corresponding hole in the ground plane to run the via through.

In the meantime, I figure I can go to 2 oz copper and thinner

traces.  I'm pretty close in routing everything (3 wires out of 350),

so figure I can get there with some care.

Not sure about some manual routing.  I don't know enough about Eagle yet.

Thanks again!!!

Dave

Hi Dave,

If you insist in 0-ohm "bridges", you might (most likely, according to your description how this is becoming complicated) want to add more than one split-resistor per net.

To get a good estimation about number of 0-ohm resistors needed, perform the following steps: (1) run autorouter, (2) highlight trace of interest, (3) count number of trace branches mixing high and low current flows. These joints are initial candidates for your 0-ohm resistors location.

BTW: I prefer (at least) partial manual routing.

Best wishes,  Ivan.

Hi Morosh,

Yes, that is where I started in my original post.  I tried doing it and it got complicated.  Maybe I'll try again.

Thanks,

Dave

On 10/06/2012 09:10, Dave Wills wrote:

My apologies if I'm being dense.

 

I don't appear to be able to change the width on any unrouted traces.  Am I missing something?

 

Manually routing some nodes doesn't seem like a good option.  If I tweak anything and need to start over, it takes a lot of time.

 

I could route the wide traces first, but I can't rip some of the traces on a node and leave others alone, then auto routed the ripped wide traces with a smaller width.  At least, not without a lot of manual work.  Seems I'd need to route wide traces, rip the ones that don't need to be wide, then change the width of the signals on that net, and finally continue routing with the new widths.  Again, this is a lot of manual work.

 

To give an idea, here are my high current nodes:

 

N$61  C21      1        P$1        3 *** up to 1 amp

          C22      1        P$1        3 *** up to 1 amp

          L3        2        2          3 *** up to 2 amps

          R24      1        P$1        3 signal level

          R25      2        P$2        3 signal level

          R26      C        P$2        3 *** up to 2 amps

          R27      2        P$2        3 signal level

          U4       9        VON        3 signal level

 

N$60   C19      2        P$2        3 signal level

          L3        1        1            3 *** up to 2 amps

          U4       11       SW         3 *** up to 1 amp

          U4       12       SW         3 *** up to 1 amp

          U4       13       SW         3 *** up to 1 amp

          U4       14       SW         3 *** up to 1 amp

          U4       15       SW         3 *** up to 1 amp

          U4       16       SW         3 *** up to 1 amp

 

N$62   Q8       4        S          3 *** up to 2 amps

          R26      A        P$1        3 *** up to 2 amps

          U5       6        -IN        3 signal level

          U7       6        -IN        3 signal level

 

N$63   Q10      4        S          3 *** up to 2 amps

          Q11      4        S          3 *** up to 2 amps

          Q8       1        D          3 *** up to 2 amps

          Q8       2        D          3 *** up to 2 amps

          Q8       5        D          3 *** up to 2 amps

          Q8       6        D          3 *** up to 2 amps

 

You can see that there are low current (skinny traces) mixed in with high current (wide) traces.  Even though the traces that need to be wide are near each other, the signal level traces get routed as wide traces.  When these need to go through vias and inner layers, it doesn't leave enough room for the rest of the signal level traces.  (Note that I have created some polygons around some of the signals, for example U4 11 - 16.  That does help routing somewhat.)

 

And then, consider the same problem when you look at GND.  I have a similar number of high current traces.  Though I have a ground plane, I need to specify some vias as larger than others into the ground plane in order to carry the current.

 

I'm starting to think that maybe Eagle isn't useful for boards with mixed trace widths and high density.  I might be better off having a professional layout firm do the last step.

 

Thanks for reading.

 

Dave

 

In your schematic, connect the non_high current nets to the high current

nets with a 0 ohm resistor, they'll have a different name.

Specify the adequate width to the high-current nets using class, route

as usual, then remove the resistor and connect directly.

there is some work in the schematic.

HTH

My apologies if I'm being dense.

I don't appear to be able to change the width on any unrouted traces.  Am I missing something?

Manually routing some nodes doesn't seem like a good option.  If I tweak anything and need to start over, it takes a lot of time.

I could route the wide traces first, but I can't rip some of the traces on a node and leave others alone, then auto routed the ripped wide traces with a smaller width.  At least, not without a lot of manual work.  Seems I'd need to route wide traces, rip the ones that don't need to be wide, then change the width of the signals on that net, and finally continue routing with the new widths.  Again, this is a lot of manual work.

To give an idea, here are my high current nodes:

N$61  C21      1        P$1        3 *** up to 1 amp
         C22      1        P$1        3 *** up to 1 amp
         L3        2        2          3 *** up to 2 amps
         R24      1        P$1        3 signal level
         R25      2        P$2        3 signal level
         R26      C        P$2        3 *** up to 2 amps
         R27      2        P$2        3 signal level
         U4       9        VON        3 signal level

N$60   C19      2        P$2        3 signal level
         L3        1        1            3 *** up to 2 amps
         U4       11       SW         3 *** up to 1 amp
         U4       12       SW         3 *** up to 1 amp
         U4       13       SW         3 *** up to 1 amp
         U4       14       SW         3 *** up to 1 amp
         U4       15       SW         3 *** up to 1 amp
         U4       16       SW         3 *** up to 1 amp

N$62   Q8       4        S          3 *** up to 2 amps
         R26      A        P$1        3 *** up to 2 amps
         U5       6        -IN        3 signal level
         U7       6        -IN        3 signal level

N$63   Q10      4        S          3 *** up to 2 amps
         Q11      4        S          3 *** up to 2 amps
         Q8       1        D          3 *** up to 2 amps
         Q8       2        D          3 *** up to 2 amps
         Q8       5        D          3 *** up to 2 amps
         Q8       6        D          3 *** up to 2 amps

You can see that there are low current (skinny traces) mixed in with high current (wide) traces.  Even though the traces that need to be wide are near each other, the signal level traces get routed as wide traces.  When these need to go through vias and inner layers, it doesn't leave enough room for the rest of the signal level traces.  (Note that I have created some polygons around some of the signals, for example U4 11 - 16.  That does help routing somewhat.)

And then, consider the same problem when you look at GND.  I have a similar number of high current traces.  Though I have a ground plane, I need to specify some vias as larger than others into the ground plane in order to carry the current.

I'm starting to think that maybe Eagle isn't useful for boards with mixed trace widths and high density.  I might be better off having a professional layout firm do the last step.

Thanks for reading.

Dave