Arbitrary Pad Shapes

OK, I think I fixed this on my 6th attempt.

What I did was to make the 4 outer rectangles 4 different pads, then make

an inner pad which abuts the 4 outer pads.  Then for that device, I connect

all 5 pads to the same pin of the symbol.

This seems to work OK but I'm confused by some things.  First, is there any

way to connect those 5 pads within the library part so that the autorouter

doesn't connect them?  The reason is all 5 pads carry high current

(discussion in another post I made) and so traces on that net class are

wider than a single pin.  Letting the autorouter connect the pins external

to the library means the wider traces have clearance errors unless I

manually make the ones that have clearance errors smaller.  (This is why I

tried the first 5 attempts at creating the part which didn't work.)

The other question is unrelated.  I have a QFN24 SMD device with an exposed

pad underneath.  The exposed pad pin is connected to GND on the schematic.

To make sure I get sufficient thermal and current transfer with the exposed

pad, I add some vias to my GND layer on the pad.  But DRC gives me overlap

errors.  The exposed pad is connected to GND and the NAME on the vias is

GND.  Why would I get overlap errors?

Thanks a ton.

Dave

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Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

On 6/27/2012 2:07 PM, Dave Wills wrote:

OK, I think I fixed this on my 6th attempt.

 

What I did was to make the 4 outer rectangles 4 different pads, then make

an inner pad which abuts the 4 outer pads.  Then for that device, I connect

all 5 pads to the same pin of the symbol.

 

This seems to work OK but I'm confused by some things.  First, is there any

way to connect those 5 pads within the library part so that the autorouter

doesn't connect them?  The reason is all 5 pads carry high current

(discussion in another post I made) and so traces on that net class are

wider than a single pin.  Letting the autorouter connect the pins external

to the library means the wider traces have clearance errors unless I

manually make the ones that have clearance errors smaller.  (This is why I

tried the first 5 attempts at creating the part which didn't work.)

Hi Dave,

The key to making the Arbitrary pad shapes is that the pad must be

completely enclosed by the polygon and any wires used to define the

arbitrary pad shape must run through the center of said pad in order to

be recognized.

A better way is to create a single small pad in the center of the giant

pad and then form the giant pad using a single polygon in the library.

All you have to do is figure out where the corners of the PAD are

located and making the polygon will be easy since you can input specific

points in the command line.

hth,

Jorge Garcia

Cadsoft Support

 

The other question is unrelated.  I have a QFN24 SMD device with an exposed

pad underneath.  The exposed pad pin is connected to GND on the schematic.

To make sure I get sufficient thermal and current transfer with the exposed

pad, I add some vias to my GND layer on the pad.  But DRC gives me overlap

errors.  The exposed pad is connected to GND and the NAME on the vias is

GND.  Why would I get overlap errors?

I'm going to answer for you here, but in the future if you wish to

present a different problem it's preferable to start a new thread. It

makes it easier when users search the forum for answers to questions.

The manual states that Overlap errors occur when copper objects of

disimilar classes come into contact with each other. Can you confirm

that all of the items belong to the GND net by typing show GND in the

command line?

hth,

Jorge Garcia

 

Thanks a ton.

 

Dave

 

On 6/27/2012 2:07 PM, Dave Wills wrote:

OK, I think I fixed this on my 6th attempt.

 

What I did was to make the 4 outer rectangles 4 different pads, then make

an inner pad which abuts the 4 outer pads.  Then for that device, I connect

all 5 pads to the same pin of the symbol.

 

This seems to work OK but I'm confused by some things.  First, is there any

way to connect those 5 pads within the library part so that the autorouter

doesn't connect them?  The reason is all 5 pads carry high current

(discussion in another post I made) and so traces on that net class are

wider than a single pin.  Letting the autorouter connect the pins external

to the library means the wider traces have clearance errors unless I

manually make the ones that have clearance errors smaller.  (This is why I

tried the first 5 attempts at creating the part which didn't work.)

Hi Dave,

The key to making the Arbitrary pad shapes is that the pad must be

completely enclosed by the polygon and any wires used to define the

arbitrary pad shape must run through the center of said pad in order to

be recognized.

A better way is to create a single small pad in the center of the giant

pad and then form the giant pad using a single polygon in the library.

All you have to do is figure out where the corners of the PAD are

located and making the polygon will be easy since you can input specific

points in the command line.

hth,

Jorge Garcia

Cadsoft Support

 

The other question is unrelated.  I have a QFN24 SMD device with an exposed

pad underneath.  The exposed pad pin is connected to GND on the schematic.

To make sure I get sufficient thermal and current transfer with the exposed

pad, I add some vias to my GND layer on the pad.  But DRC gives me overlap

errors.  The exposed pad is connected to GND and the NAME on the vias is

GND.  Why would I get overlap errors?

I'm going to answer for you here, but in the future if you wish to

present a different problem it's preferable to start a new thread. It

makes it easier when users search the forum for answers to questions.

The manual states that Overlap errors occur when copper objects of

disimilar classes come into contact with each other. Can you confirm

that all of the items belong to the GND net by typing show GND in the

command line?

hth,

Jorge Garcia

 

Thanks a ton.

 

Dave

 

Jorge Garcia wrote on Wed, 27 June 2012 14:19

On 6/27/2012 2:07 PM, Dave Wills wrote:

<snip>

Hi Dave,

 

The key to making the Arbitrary pad shapes is that the pad must be

completely enclosed by the polygon and any wires used to define the

arbitrary pad shape must run through the center of said pad in order to

 

be recognized.

 

A better way is to create a single small pad in the center of the giant

 

pad and then form the giant pad using a single polygon in the library.

 

All you have to do is figure out where the corners of the PAD are

located and making the polygon will be easy since you can input

specific

points in the command line.

 

hth,

Jorge Garcia

Cadsoft Support

<snip>

I'm going to answer for you here, but in the future if you wish to

present a different problem it's preferable to start a new thread. It

makes it easier when users search the forum for answers to questions.

 

The manual states that Overlap errors occur when copper objects of

disimilar classes come into contact with each other. Can you confirm

that all of the items belong to the GND net by typing show GND in the

command line?

 

hth,

Jorge Garcia

 

Hi Jorge,

WRT polygons, I think this gets me back to the problems I reported to

start.  Polygons have width and the width will have to be less than the pad

size in order to include the fingers of the "H" (or overlap).  So unless

the polygon has near zero width, the fingers will have rounded corners.

I'll try again to see what I come up with.  Regardless, I think I end up

with errors/warnings that can't be resolved, just approved.

WRT the GND net, yes, if I show GND, the vias, the exposed pad and the GND

layer all show up.  The name of the pin on the package is EXP and it is

connected to GND with a wire.  The net list shows that pin of the IC

connected to GND.

Thanks,

Dave

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.