Wot, still no package land pattern vias?

On 19/09/2014 2:58 p.m., Ryan Pettigrew wrote:

The one thing I expected to be fixed in v7 was vias in land patterns.

Nope, still AWOL, in spite of a glaring need for thermal transfer to

ground via the center pad on some parts. What gives? When is this

coming?

Hi Ryan

Since version 6 you have been able to create arbitrary pad shapes.

Search for that in the HELP if you have over looked it.

If you mean a via in a SMD without getting a DRC error or no DRC

checking between objects within the package, I think that is yet to arrive.

HTH

Warren

"warrenbrayshaw"  skrev i nyhetsmeldingen: lvgk7v$oqv$1@cheetah.cadsoft.de

...

On 19/09/2014 2:58 p.m., Ryan Pettigrew wrote:

The one thing I expected to be fixed in v7 was vias in land patterns.

Nope, still AWOL, in spite of a glaring need for thermal transfer to

ground via the center pad on some parts. What gives? When is this

coming?

Since version 6 you have been able to create arbitrary pad shapes. Search

for that in the HELP if you have over looked it.

If you mean a via in a SMD without getting a DRC error or no DRC checking

between objects within the package, I think that is yet to arrive.

He is talking about thermal VIA. A via under the IC just to conduct heat to

the pcb.. You can do this today by defining them as a thermal IO pins. V7

lets you merge all those pads into a single symbol pin.

CadSoft Guest wrote:

 

He is talking about thermal VIA. A via under the IC just to conduct heat to

the pcb.

Indeed I am. Put another way, a via under the IC to conduct heat away from the IC.

CadSoft Guest wrote:

 

You can do this today by defining them as a thermal IO pins. V7

lets you merge all those pads into a single symbol pin.

Ah, but will the via be on the via layer, where it belongs?

On 20/09/2014 12:43 p.m., Ryan Pettigrew wrote:

CadSoft Guest wrote:

 

 

 

He is talking about thermal VIA. A via under the IC just to conduct

heat to

 

the pcb.

Indeed I am. Put another way, a via under the IC to conduct heat away

from the IC.

 

CadSoft Guest wrote:

 

 

 

You can do this today by defining them as a thermal IO pins. V7

 

lets you merge all those pads into a single symbol pin.

Ah, but will the via be on the via layer, where it belongs?

 

There is a wee bit of confusion happening here due to terminology.

I'll try to clarify.

Only on a board can you add a VIA(mouse over the icon to confirm). When

you add that VIA you can control the layers that VIA goes between.

Choices are governed by the  layer specification you previously set in

the DRC.

The VIA is said to be on the display layer 'VIA' hence you can control

it's visibility.

In the library you create a package but you don't have access to vias

there.  You have the similar looking icon that is PAD. (mouse over the

icon to confirm) This is a through hole pad (PTH) the drill of which

will always go all the way through the board.

Scenario 1:

If you are happy to have holes all the way through the board you can

conduct the heat to the other side of the board or disperse it to any

inner layer copper area that an inner restring of the PTH can connect

to. You can build all of this into a package using PADS as fake vias.

Scenario 2:

If you need a thermal connector that goes between layer Top an inner

layer of a multi layer board you would need to use a via approach as a

via is the only object that has these properties.

I cannot see a way to do this currently.

If, in the board editor, you place a via onto a standalone polygon, the

polygon of an arbitrary pad or an SMD created in a package, you get an

overlap error when the DRC is run.

You can of course draw a signal polygon onto the board and add vias with

the same name onto it. No DRC errors arise when you do this but thats

not we want to have to do. It should all be able to be setup in the library.

Let me know if I have missed something

Warren

On 20/09/2014 12:43 p.m., Ryan Pettigrew wrote:

CadSoft Guest wrote:

 

 

 

He is talking about thermal VIA. A via under the IC just to conduct

heat to

 

the pcb.

Indeed I am. Put another way, a via under the IC to conduct heat away

from the IC.

 

CadSoft Guest wrote:

 

 

 

You can do this today by defining them as a thermal IO pins. V7

 

lets you merge all those pads into a single symbol pin.

Ah, but will the via be on the via layer, where it belongs?

 

There is a wee bit of confusion happening here due to terminology.

I'll try to clarify.

Only on a board can you add a VIA(mouse over the icon to confirm). When

you add that VIA you can control the layers that VIA goes between.

Choices are governed by the  layer specification you previously set in

the DRC.

The VIA is said to be on the display layer 'VIA' hence you can control

it's visibility.

In the library you create a package but you don't have access to vias

there.  You have the similar looking icon that is PAD. (mouse over the

icon to confirm) This is a through hole pad (PTH) the drill of which

will always go all the way through the board.

Scenario 1:

If you are happy to have holes all the way through the board you can

conduct the heat to the other side of the board or disperse it to any

inner layer copper area that an inner restring of the PTH can connect

to. You can build all of this into a package using PADS as fake vias.

Scenario 2:

If you need a thermal connector that goes between layer Top an inner

layer of a multi layer board you would need to use a via approach as a

via is the only object that has these properties.

I cannot see a way to do this currently.

If, in the board editor, you place a via onto a standalone polygon, the

polygon of an arbitrary pad or an SMD created in a package, you get an

overlap error when the DRC is run.

You can of course draw a signal polygon onto the board and add vias with

the same name onto it. No DRC errors arise when you do this but thats

not we want to have to do. It should all be able to be setup in the library.

Let me know if I have missed something

Warren

CadSoft Guest wrote:

 

Let me know if I have missed something

Yes, apparently, you have; notably, that the title of this part of the forum is "EAGLE Suggestions", and not "EAGLE Help". I'm not asking how to work around the problem of vias not being available in Land Patterns. I'm asking why the feature is still missing after a major version change.

CadSoft Guest wrote:

 

In the library you create a package but you don't have access to vias

there.

Yes, this is the feature that is missing. I want it to no longer be missing, so that it is no longer necessary to work around it.

CadSoft Guest wrote:

 

Scenario 1:

If you are happy to have holes all the way through the board you can

conduct the heat to the other side of the board or disperse it to any

inner layer copper area that an inner restring of the PTH can connect

to. You can build all of this into a package using PADS as fake vias.

Why would I want the PCB manufacturer to make a fake via when I want them to make a real via? Furthermore, isn't this just unnecessarily confusing to the PCB manufacturer, and ultimately, a less reliable way of getting the required board feature? Of course I'm not happy with having holes all the way through the board on the center pad of a surface mount part; that's why I want a tented and filled via there.

Your attempts to help would be better spent in supporting the request for the missing feature.