Wot, still no package land pattern vias?

On 19/09/2014 2:58 p.m., Ryan Pettigrew wrote:

The one thing I expected to be fixed in v7 was vias in land patterns.

Nope, still AWOL, in spite of a glaring need for thermal transfer to

ground via the center pad on some parts. What gives? When is this

coming?

Hi Ryan

Since version 6 you have been able to create arbitrary pad shapes.

Search for that in the HELP if you have over looked it.

If you mean a via in a SMD without getting a DRC error or no DRC

checking between objects within the package, I think that is yet to arrive.

HTH

Warren

"warrenbrayshaw"  skrev i nyhetsmeldingen: lvgk7v$oqv$1@cheetah.cadsoft.de

...

On 19/09/2014 2:58 p.m., Ryan Pettigrew wrote:

The one thing I expected to be fixed in v7 was vias in land patterns.

Nope, still AWOL, in spite of a glaring need for thermal transfer to

ground via the center pad on some parts. What gives? When is this

coming?

Since version 6 you have been able to create arbitrary pad shapes. Search

for that in the HELP if you have over looked it.

If you mean a via in a SMD without getting a DRC error or no DRC checking

between objects within the package, I think that is yet to arrive.

He is talking about thermal VIA. A via under the IC just to conduct heat to

the pcb.. You can do this today by defining them as a thermal IO pins. V7

lets you merge all those pads into a single symbol pin.

CadSoft Guest wrote:

 

He is talking about thermal VIA. A via under the IC just to conduct heat to

the pcb.

Indeed I am. Put another way, a via under the IC to conduct heat away from the IC.

CadSoft Guest wrote:

 

You can do this today by defining them as a thermal IO pins. V7

lets you merge all those pads into a single symbol pin.

Ah, but will the via be on the via layer, where it belongs?

On 20/09/2014 12:43 p.m., Ryan Pettigrew wrote:

CadSoft Guest wrote:

 

 

 

He is talking about thermal VIA. A via under the IC just to conduct

heat to

 

the pcb.

Indeed I am. Put another way, a via under the IC to conduct heat away

from the IC.

 

CadSoft Guest wrote:

 

 

 

You can do this today by defining them as a thermal IO pins. V7

 

lets you merge all those pads into a single symbol pin.

Ah, but will the via be on the via layer, where it belongs?

 

There is a wee bit of confusion happening here due to terminology.

I'll try to clarify.

Only on a board can you add a VIA(mouse over the icon to confirm). When

you add that VIA you can control the layers that VIA goes between.

Choices are governed by the  layer specification you previously set in

the DRC.

The VIA is said to be on the display layer 'VIA' hence you can control

it's visibility.

In the library you create a package but you don't have access to vias

there.  You have the similar looking icon that is PAD. (mouse over the

icon to confirm) This is a through hole pad (PTH) the drill of which

will always go all the way through the board.

Scenario 1:

If you are happy to have holes all the way through the board you can

conduct the heat to the other side of the board or disperse it to any

inner layer copper area that an inner restring of the PTH can connect

to. You can build all of this into a package using PADS as fake vias.

Scenario 2:

If you need a thermal connector that goes between layer Top an inner

layer of a multi layer board you would need to use a via approach as a

via is the only object that has these properties.

I cannot see a way to do this currently.

If, in the board editor, you place a via onto a standalone polygon, the

polygon of an arbitrary pad or an SMD created in a package, you get an

overlap error when the DRC is run.

You can of course draw a signal polygon onto the board and add vias with

the same name onto it. No DRC errors arise when you do this but thats

not we want to have to do. It should all be able to be setup in the library.

Let me know if I have missed something

Warren

CadSoft Guest wrote:

 

Let me know if I have missed something

Yes, apparently, you have; notably, that the title of this part of the forum is "EAGLE Suggestions", and not "EAGLE Help". I'm not asking how to work around the problem of vias not being available in Land Patterns. I'm asking why the feature is still missing after a major version change.

CadSoft Guest wrote:

 

In the library you create a package but you don't have access to vias

there.

Yes, this is the feature that is missing. I want it to no longer be missing, so that it is no longer necessary to work around it.

CadSoft Guest wrote:

 

Scenario 1:

If you are happy to have holes all the way through the board you can

conduct the heat to the other side of the board or disperse it to any

inner layer copper area that an inner restring of the PTH can connect

to. You can build all of this into a package using PADS as fake vias.

Why would I want the PCB manufacturer to make a fake via when I want them to make a real via? Furthermore, isn't this just unnecessarily confusing to the PCB manufacturer, and ultimately, a less reliable way of getting the required board feature? Of course I'm not happy with having holes all the way through the board on the center pad of a surface mount part; that's why I want a tented and filled via there.

Your attempts to help would be better spent in supporting the request for the missing feature.

On 9/18/2014 10:58 PM, Ryan Pettigrew wrote:

The one thing I expected to be fixed in v7 was vias in land patterns.

Nope, still AWOL, in spite of a glaring need for thermal transfer to

ground via the center pad on some parts. What gives? When is this

coming?

 

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Hi Ryan,

This is already possible. Here's what you would do:

In the package:

1. Place the thermal transfer through-hole pads(pads and vias are

physically the same thing, the distinction we make in EAGLE is that pads

are always associated with components and go through the hole board,

vias are on the board and generally associated with transitions between

layers).

2. Draw polygons enclosing these pads on the Top, Bottom, tStop, bStop,

tCream, and bCream layers. My assumption here is that the thermal pad

shows up on both sides of the board, this isn't always the case but for

the sake of generality I've included them here.

3. In the device editor, assign all of those pads to the same pin of

your symbol, because they're within the boundaries of the polygon the

polygon is considered an extension of those pads.

That's pretty much all you have to do, and EAGLE will handle it without

errors. Section 8.14 of the EAGLE manual covers this in greater

detail.The Help pages for PAD and SMD provide more details

hth,

Jorge Garcia

CadSoft Guest wrote:

 

That's pretty much all you have to do, and EAGLE will handle it without

errors. Section 8.14 of the EAGLE manual covers this in greater

detail.The Help pages for PAD and SMD provide more details

Jorge, the problem is, you can't then assign it to the via layer, with all the other vias, where it belongs, and where it is convenient for the board assembler to find it, and know what it is, and what its purpose is supposed to be.

I reiterate; I am NOT interested in ways of working around this problem; I am interested in this problem being fixed, so no workaround is required. If I wanted help getting around this limitation in the software, I would have posted in the help forum, not here in the suggestion forum.

"Ryan Pettigrew"  skrev i nyhetsmeldingen:

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Jorge, the problem is, you can't then assign it to the via layer, with

all the other vias, where it belongs, and where it is convenient for the

board assembler to find it, and know what it is, and what its purpose is

supposed to be.

I do not see the need to differ those vias/pads from other vias/pads. Maybe

you can explain why they need to know? Full through vias and pads are

generally manufactured in the same process afaik.

The only valid argument I can see is that sometimes, when working with

blind/buried/micro-vias, you may want the heat transfer between controlled

layers, but doing this in a library editor is not straight forward. It could

be done with some "vitrual via" placement that needs to be placed manually

in the board design, and would cause a DRC error if not present.

On 9/22/2014 7:41 PM, Ryan Pettigrew wrote:

 

Jorge, the problem is, you can't then assign it to the via layer, with

all the other vias, where it belongs, and where it is convenient for the

board assembler to find it, and know what it is, and what its purpose is

supposed to be.

 

Hi Ryan,

I'm afraid I disagree, thermal vias within a package don't need to be on

the vias layer. The distinction between pads and vias is something

internal to EAGLE. When we generate gerber output, through-hole pads and

vias are always included together, so they're indistinguishable to the

board house. Even visually within EAGLE they're indistinguishable

because the pads and vias layers use the same color.

Has the assembler given any special instruction or complaint?

hth,

Jorge Garcia

On 24/09/2014 4:11 a.m., Jorge Garcia wrote:

A few 'not trues' here

 

I'm afraid I disagree, thermal vias within a package don't need to be on

the vias layer.

They do if you don't want drills all the way through the PCB

  The distinction between pads and vias is something

internal to EAGLE. When we generate gerber output, through-hole pads and

vias are always included together,  so they're indistinguishable to the

board house.

True when talking of the copper for a layer but un-true  when talking

drills for a multi layer board.

There should be additional drill files for the holes that go between

particular layers.

Even visually within EAGLE they're indistinguishable

because the pads and vias layers use the same color.

Not when you specify the colour as the background colour. Then the

layers they go between makes them visually different

 

Has the assembler given any special instruction or complaint?

Eagle's age is becoming an issue. I'm not talking of GUI's or WOW tools

like 3D but rather not having keep up with the demands placed on the

designer by reducing geometries of components and board size. There are

a few basics that have been suggested repeatedly. I feel it will be the

failure to deliver these that will reduce the Eagle market share. Sure

add new features the marketing people can use but this should be

balanced by correcting some basic short comings so the product remains

solid and not let down by these deficiencies.

 

hth,

Jorge Garcia

 

HTH

Warren