GND pads not connecting to GND polygon?

On 31.05.2016 13:11, Nuno Gomes wrote:

Hi, I'm trying to create a 4 layer PCB (TOP + POWER + GND + BOTTOM). I created 2 planes for the VBB and GNDBB using polygons.

My problem is the connection (let's say) beetween a resistor and the PAD of a component (let's call it X component). If try to connect the VBB connection of the resistor to a Via (and the via's name is VBB) the VBB PAD of the X component with appear like the pic below and the airwire that was connecting the resistor to the X component is gone!

But if I try to do the same with a resistor that is connected to a GND pad, the pad stays the same and the airwire is still there, which makes me wonder if the vias are even connecting to the GND plan.

 

The following are printscreens of the settings I'm currently using.

 

What am I doing wrong here?

Any help would be highly appreciated!

I'm not sure I understand the question.

Just make sure the through hole GND pad is surrounded by a polygon named

GND. A SMD resistor pad needs a via closeby to get to inner layer.

And remember to do ratsnest.

So, the GND pad on the X component? Like JP2 component on the last picture?

On 31.05.2016 13:29, Nuno Gomes wrote:

So, the GND pad on the X component? Like JP2 component on the last picture?

Are you referring to pin10 of JP2? (assuming pin1 is square) What

netname does that airwire belonging to? Pin1 of JP2 looks connected to

GND (assuming hatched grey layer is Layer 15 and polygon named GND)

You dont seem to have any other polygon on any layer under the connectors.

Pin1 on JP2 looks a bit funny too. Its appears connected to GND, but

still got a blue wire.

On 31.05.2016 13:35, Morten Leikvoll wrote:

On 31.05.2016 13:29, Nuno Gomes wrote:

So, the GND pad on the X component? Like JP2 component on the last

picture?

 

Are you referring to pin10 of JP2? (assuming pin1 is square) What

netname does that airwire belonging to? Pin1 of JP2 looks connected to

GND (assuming hatched grey layer is Layer 15 and polygon named GND)

 

You dont seem to have any other polygon on any layer under the connectors.

 

Pin1 on JP2 looks a bit funny too. Its appears connected to GND, but

still got a blue wire.

 

Ok, maybe the colors are a bit hard to separate.. I see some darker grey

below the hatched..  I suspect it has a different netname than the airwire.

Also, I think you need to do better routing on this. My initial reaction

is that this needs some proper engineering. Like proper decoupling,

proper heatsinking and proper widths for higher currents here and there.

Those lower chips looks like power hungry chips.

The pin10 of the JP2 is indeed the GND. This is what the device looks like:

Yes, the hatched grey layer is layer 15 and the polygon is named GNDBB because there are two tipes of GND plan and two power plans (GND + VDD3.3 & GNDBB + VBB) the GNDBB + VBB are two polygons on top of each other and are the ones closer to the border of the PCB.

In the last pic of the original question there are indeed two layers on top of each other, not sure if that's the problem.
I'm not sure about what you "said " Pin1 of JP2 looks connected to GND" because the pin 1 is the POWER (square pad) and it's connected to VBB.

On 31.05.2016 13:47, Nuno Gomes wrote:

The pin10 of the JP2 is indeed the GND. This is what the device looks like:

Yes, the hatched grey layer is layer 15 and the polygon is named GNDBB because there are two tipes of GND plan and two power plans (GND + VDD3.3 & GNDBB + VBB) the GNDBB + VBB are two polygons on top of each other and are the ones closer to the border of the PCB.

In the last pic of the original question there are indeed two layers on top of each other, not sure if that's the problem.

I'm not sure about what you "said " Pin1 of JP2 looks connected to GND" because the pin 1 is the POWER (square pad) and it's connected to VBB.

Pin1 of JP1 just looks funny. Or maybe its the blue wire that goes from

there to the capacitor. I would expect to get this signal from a via

down to the polygon instead of routing all the way to the pin.

Did you check what name the airwire got? Maybe its not connected to what

you expect. Have a look at the schematic and try moving JP2 around to

check if its pins are connected to what it looks like.

On 31.05.2016 14:15, Morten Leikvoll wrote:

On 31.05.2016 13:47, Nuno Gomes wrote:

The pin10 of the JP2 is indeed the GND. This is what the device looks

like:

Yes, the hatched grey layer is layer 15 and the polygon is named GNDBB

because there are two tipes of GND plan and two power plans (GND +

VDD3.3 & GNDBB + VBB) the GNDBB + VBB are two polygons on top of each

other and are the ones closer to the border of the PCB.

In the last pic of the original question there are indeed two layers

on top of each other, not sure if that's the problem.

I'm not sure about what you "said " Pin1 of JP2 looks connected to

GND" because the pin 1 is the POWER (square pad) and it's connected to

VBB.

 

Pin1 of JP1 just looks funny. Or maybe its the blue wire that goes from

there to the capacitor. I would expect to get this signal from a via

down to the polygon instead of routing all the way to the pin.

 

Did you check what name the airwire got? Maybe its not connected to what

you expect. Have a look at the schematic and try moving JP2 around to

check if its pins are connected to what it looks like.

An alternative way is to click the show button, then the airwire. Both

the airwire and the polygon should highlite. If not, they are not the

same net.

About the engineering of the routes I have to say that I only started manually optimizing the JP2 and it's conenctions and everything else you are seeing has been done by autoroute (there's still long way to go )
About the pin 1 of JP1 the autoroute did it automatically.
About that JP2 pin 10 airwire (GNDBB connection) seems like it's gone since I ran ratsnest (dunno why xd)

And when I click the show button and click the GND routes it also highlights the GND polygon so I think it's done right. What do you think?

EDIT:

what do you mean by

"Like proper decoupling, proper heatsinking..."

On 31/05/16 12:11, Nuno Gomes wrote:

I created 2 planes for the VBB and GNDBB using polygons.

Note----

^^^^^

But if I try to do the same with a resistor that is connected to a GND pad,

Note----

^^^

the pad stays the same and the airwire is still there, which makes me wonder if the vias are even connecting to the GND plan.

If your ground plane polygon is named "GNDBB" it will not connect to

vias named "GND". They need to be the same.