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OPA569 libary

steve999

Evening all

 

Anybody got a library for a texas inst OPA569 ?

 

http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=opa569&fileType=pdf

 

had a go making it myself but struggling with the heat pad and via's

 

Steve

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  • 0

    Am 08.06.2016 um 22:32 schrieb stephen clarke:

    Evening all

     

    Anybody got a library for a texas inst OPA569 ?

     

    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=opa569&fileType=pdf

     

    had a go making it myself but struggling with the heat pad and via's

     

    Steve

     

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    Why don't you place here what you have done already so we can help you?

     

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    Mit freundlichen Grüßen / With best regards

     

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  • 0 in reply to autodeskguest

    thank you for the response

     

    Sorry i have been busy at work

    image

     

    i am struggling a bit with the following

     

    Page 19 fig 16 and 18 shows the recommended pcb layout.

     

    Fig 16 shows that a thermal pad should be under the ic (highlighted in green) with a exposed area for contact with the ic pad, it further states that it is recommended that this pad is double sided and connected by via's. the via sizes are given this is for wicking on the solder process. there should be another 4 in the corners i presume this is for thermal bonding of the two copper area's this pad should be connected to pins 1,10,11,20.

     

    I am not sure on how to go about this going to have another go this weekend.

     

    i am also unsure of how to go about the connections for the following pins as the above fig 18 shows large copper area's

     

    Pins 12,13 V+

    Pins 14,15 Output

    Pins 17,18 V-

     

    Thank you

     

    Steve

  • 0 in reply to steve999

    Hi Steve,

     

    Okay this is actually a really common thing, I've done loads of IC's which are similar. Basically in your library part, place the pads for the component legs and the 140 mils x 176 mils thermal area as SMT pads. Give the thermal pad a useful name like EPAD and give it a corresponding pin on the symbol. Usually these are meant to be tied to 0V but check your datasheet. This is all you need to do in your library for this part. Then in your layout you can add polygons and vias for the rest. So for your V+, Output and V- connections you will draw polygons and give them those names so they connect, remembering to turn off thermals in the properties. For the thermal areas add polygons under the IC on both sides of the board with the same name as your EPAD's net name (and on inner layers too if so desired) and then add via's with the drill size specified in the datasheet, again with the same name as your EPAD's net.

     

    You will likely get some DRC warnings about the vias in your pads under the IC, you can approve them so they don't show up again.

     

    Best Regards,

     

    Rachael

  • 0 in reply to steve999

    Hi Steve,

     

    Yes no problem but I can't send you a pm until approve my contact request.

     

    Best Regards,


    Rachael

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