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Flooded Polygon

angelus9

I have an RF design with a RF Power Amp on the board.  I has a GND/thermal pad under an SOIC8 package.

 

In the library part I made, I put the ground pad in the footprint plus I have eight through holes in the ground pad to conduct heat away from the part plus connect the other layer's grounds to this pad.

 

This is a 4 layer PCB.

 

Problems:

 

1) In the library, I would like to name the pad plus the eight through holes to EGND so the ground floods everything and there is no gaps in the ground plane.  Eagle requires all pads to be named uniquely.  I tried EGND@1, EGND@2, etc.  Didn't help.

 

2) So when I  ratsnest the polygons (EGND), clearances are created between the 7 pads named EGND@1, EGND@2.  The one pad named EGND is flooded/connected but the other 7 pads aren't.  The GND under the SOIC has clearances created by the ratnest command, I must have solid flooding of this pad to the polygon EGND.

 

I tried putting a Rectangle over this area which works until your ratsnest again.  So I ratnest first, add the rectangle, then run CAM.  Low and behold the CAM functions ratsnests again and creates new clearances.

 

Ready to run board but this is holding me up.

 

How can I fix this?

 

Thanks,

Don

  • 0

    If you attached your library it would be easier to see where you have gone

    wrong and provide a solution.

     

    Warren

     

     

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

  • 0 in reply to autodeskguest

    I tried uploading the library but it says "file type not allowed."  Tried to Zip it, same thing.

     

    Any sugestions?

     

    See the MAX2601ESA+ part if I can find a way to upload the library.

     

    Thanks,

    Don

  • 0 in reply to angelus9

    Yes, that Element14 site is a bundle of p**! It's only a front end to the

    real forums at Cadsoft which is a newsgroup so you could go directly there

    and post up to 40k file. Or if you like a browser front end you could go to

    EagleCentral, which is also a front end but brilliant. Down side with

    EagleCentral is you need to apply to post there and it takes a day for

    James to set you up. 

     

     

    There are two ways of getting attachments done at Element14. Attachments

    and in-line so make sure you are using the attachment method for a library

    file.

     

    HTH

    Warren

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

  • 0

    On 08/06/2013 05:40 PM, Don Golding wrote:

    I have an RF design with a RF Power Amp on the board.  I has a

    GND/thermal pad under an SOIC8 package.

     

    In the library part I made, I put the ground pad in the footprint plus I

    have eight through holes in the ground pad to conduct heat away from the

    part plus connect the other layer's grounds to this pad.

     

    This is a 4 layer PCB.

     

    Problems:

     

    1) In the library, I would like to name the pad plus the eight through

    holes to EGND so the ground floods everything and there is no gaps in

    the ground plane.  Eagle requires all pads to be named uniquely.  I

    tried EGND@1, EGND@2, etc.  Didn't help.

     

    I just did a similar part. Here's what I did:

     

    In the library, lay out the ground/thermal pad as an SMD that covered

    the full dimensions with a roundness of 0%. I called it "DIEPAD". I

    didn't try placing any vias or pads in it, as there's nothing about the

    device that requires them to be in specific locations.

     

    Place the component in the schematic and connect DIEPAD to GND.

     

    Place the device on the board. You'll see an airwire from DIEPAD to the

    nearest GND point. Add vias where appropriate. Change the name of the

    vias to "GND" and connect one of them to the pad SMD.

     

    When you next do a DRC check you'll get a warning about insufficient

    clearance between the via and the signal. You can either approve the DRC

    violation, or you can go into the DRC rules and change the minimum

    clearance from an SMD to a via of the same signal to zero. I did the latter.

     

    Double check that you don't somehow end up with solder mask on your pad,

    and that everything else looks right.

     

    2) So when I  ratsnest the polygons (EGND), clearances are created

    between the 7 pads named EGND@1, EGND@2.  The one pad named EGND is

    flooded/connected but the other 7 pads aren't.  The GND under the SOIC

    has clearances created by the ratnest command, I must have solid

    flooding of this pad to the polygon EGND.

     

    Are these "Clearances" complete isolation, or are they thermals? If

    they're totally isolated, make sure you've connected each of the pads

    (EGND@1, EGND@2, etc.) to EGND in the schematic. If they're thermals, go

    into the library, bring up the part's package, and change the "Thermals"

    to "Off" for those pads.

     

    -Reece

     

  • 0

    Can you answer this question?

     

    How can you have mulitiple pins on a part (say GND pins) connect to a polygon flood called GND.  Note Pins 2,6,7 and PAD must all be tied to a GND flood.  The pad transfers heat out of the chip so there should be a wide solid flood to the pad and these pins.  When making a part in the library, Eagle won't let you NAME multiple pins the same name which would take care of this problem.

     

    I created a new library with just this part in it an it won't let me upload it (only 5K).

     

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