Flooded Polygon

Question

I have an RF design with a RF Power Amp on the board. I has a GND/thermal pad under an SOIC8 package.

In the library part I made, I put the ground pad in the footprint plus I have eight through holes in the ground pad to conduct heat away from the part plus connect the other layer's grounds to this pad.

This is a 4 layer PCB.

Problems:

1) In the library, I would like to name the pad plus the eight through holes to EGND so the ground floods everything and there is no gaps in the ground plane. Eagle requires all pads to be named uniquely. I tried EGND@1, EGND@2, etc. Didn't help.

2) So when I ratsnest the polygons (EGND), clearances are created between the 7 pads named EGND@1, EGND@2. The one pad named EGND is flooded/connected but the other 7 pads aren't. The GND under the SOIC has clearances created by the ratnest command, I must have solid flooding of this pad to the polygon EGND.

I tried putting a Rectangle over this area which works until your ratsnest again. So I ratnest first, add the rectangle, then run CAM. Low and behold the CAM functions ratsnests again and creates new clearances.

Ready to run board but this is holding me up.

How can I fix this?

Thanks,

Don

autodeskguest · Accepted Answer

On 08/06/2013 05:40 PM, Don Golding wrote: I have an RF design with a RF Power Amp on the board. I has a GND/thermal pad under an SOIC8 package. In the library part I made, I put the ground pad in the footprint plus I have eight through holes in the ground pad to conduct heat away from the part plus connect the other layer's grounds to this pad. This is a 4 layer PCB. Problems: 1) In the library, I would like to name the pad plus the eight through holes to EGND so the ground floods everything and there is no gaps in the ground plane. Eagle requires all pads to be named uniquely. I tried EGND@1, EGND@2, etc. Didn't help. I just did a similar part. Here's what I did: In the library, lay out the ground/thermal pad as an SMD that covered the full dimensions with a roundness of 0%. I called it "DIEPAD". I didn't try placing any vias or pads in it, as there's nothing about the device that requires them to be in specific locations. Place the component in the schematic and connect DIEPAD to GND. Place the device on the board. You'll see an airwire from DIEPAD to the nearest GND point. Add vias where appropriate. Change the name of the vias to "GND" and connect one of them to the pad SMD. When you next do a DRC check you'll get a warning about insufficient clearance between the via and the signal. You can either approve the DRC violation, or you can go into the DRC rules and change the minimum clearance from an SMD to a via of the same signal to zero. I did the latter. Double check that you don't somehow end up with solder mask on your pad, and that everything else looks right. 2) So when I ratsnest the polygons (EGND), clearances are created between the 7 pads named EGND@1, EGND@2. The one pad named EGND is flooded/connected but the other 7 pads aren't. The GND under the SOIC has clearances created by the ratnest command, I must have solid flooding of this pad to the polygon EGND. Are these "Clearances" complete isolation, or are they thermals? If they're totally isolated, make sure you've connected each of the pads (EGND@1, EGND@2, etc.) to EGND in the schematic. If they're thermals, go into the library, bring up the part's package, and change the "Thermals" to "Off" for those pads. -Reece