Stopping TO-220 isolation

On 25/12/2014 3:51 p.m., Steve Ins wrote:

I have a problem which is keeping me working over the holiday -the only

thing keeping my board from fab. I've "tried everything" and read

every Googled forum, but can't find the problem addressed (everyone

wants to insulate their TO-220, not the other way around).

 

I have a 7805 in a TO-220 and I want the bolt hole connected directly to

the ground plane ("GND") on the bottom (and the top). Eagle insists on

isolating it. It seems Eagle has lots of ways to keep traces apart, but

no ways to insist "I WANT COPPER HERE NO MATTER WHAT". I've edited the

part, but to no avail; packages only have holes, not vias. I've even

tried illegal ways, such as putting a hole on a via (didn't work). I've

messed with all the DRC's (usually with bad consequences), but even that

didn't fix it. If I can't solve this, I can always edit the Gerbers...

p.s. NEVER had this problem with Bishop Graphics and Datak...

 

Hi. One way to do it, assuming you do not wish to create a four pin device.

Make the library package a three pin device and ignore the tab as that

will be your copper pour on the top and bottom layer. Also on a user

defined layer mark the position where the screw hole should be located.

This will be the location you place a via at on the board.

When you edit the board, route pins 1 thru 3 normally.

Place a via at the location you marked in the package. Name the via GND.

Place your GND polygons and then RATSNEST.

It should all look as you desire. The board house will make the screw

hole a plated through via as there is copper top and bottom.

HTH

Warren

I think from Eagle 6 upwards you can use the arbitrary pad shape

function and just add a polygon to the gnd tab. The 4 pad device should

work, just make sure when you create the part that in the connect dialog

you connect Pad2 and the new ground tab pad 4 to the same GND pin in the

schematic symbol.

Merry Xmas

Steve Ins pisze:

I have a problem which is keeping me working over the holiday -the only

thing keeping my board from fab. I've "tried everything" and read

every Googled forum, but can't find the problem addressed (everyone

wants to insulate their TO-220, not the other way around).

 

I have a 7805 in a TO-220 and I want the bolt hole connected directly to

the ground plane ("GND") on the bottom (and the top). Eagle insists on

isolating it. It seems Eagle has lots of ways to keep traces apart, but

no ways to insist "I WANT COPPER HERE NO MATTER WHAT". I've edited the

part, but to no avail; packages only have holes, not vias. I've even

tried illegal ways, such as putting a hole on a via (didn't work). I've

messed with all the DRC's (usually with bad consequences), but even that

didn't fix it. If I can't solve this, I can always edit the Gerbers...

p.s. NEVER had this problem with Bishop Graphics and Datak...

The easiest way is to put manually few GND wires over the mounting hole.

And accept few DRC errors.

Eagle avoids any copper around holes and other elements with lines in

dimension layer - the program sets a "gap" with "clearance" width.

This is very known feature (IMHO a bug) Eagle uses dimension as a

conductive element until you set distance copper-dimension to zero. But

in this case you have to set proper isolate of the polygon.

HTH

--

Grzegorz Zalot

complex ltd.

office tel/fax : +48 32 2505840

mobil : +48 501 301515

Warren: I figure I could do it by making it 4-terminal, but that just seems so... yuk. Unfortunately, I could not get your method to work. On the board I am only allowed to place vias on layer "1-16", not on user-defined layers. At the package level, I cannot even create vias. Was this user-defined layer (i.e. layer 200) to be done at the package or board level? I tried placing a via directly under the bolt hole, but that overrode the bolt size and made the bolt hole the via diamater.

Merry Xmas: It works, but it does make my library device specific to this PC board since it depends on how I routed around the pins, since the polygon must enclose the GND pin. It also gives "Package ... contains an invalid polygon." whenever I ratsnest.

Grzegorz: It worked! When I tried this before, it didn't. Now I know why: The wire MUST start at or end at a GND via, not just cross over, not just connect to the GND plane, not go to a non-GND via. ALSO it must NOT start or end at the bolt center or you will get the dreaded "Can't backannotate this operation. Please do this in the schematic!" This doesn't require messing with design rules or packages. As far as a few DRC violations, Damn the torpedos!