How can I change the width of thermal ties

Use a small piece of wire with the desired width & use the name of the

signal that is connected to the smd-pad

r

You can also change the width of the polygon, but this will affect all

thermals

r

On Tue, 30 Jun 2009 23:40:27 +0200, "Ing. J.M. Rafetseder"

<jrafetseder@hotmail.com> wrote:

You can also change the width of the polygon, but this will affect all

thermals

r

 

I should have mentioned, but the GND polygon width is 12 mils and the

isolate value is 10 mils.  Well, if I place tRestrict wires around the GND

pad, then I could use a small trace to connect the pad to the polygon, but

that's a lot of work since I have to do this for 16 circuits.  I was hoping

for a simpler way to do this.

-Dave Pollum

On Tue, 30 Jun 2009 23:40:27 +0200, "Ing. J.M. Rafetseder"

<jrafetseder@hotmail.com> wrote:

You can also change the width of the polygon, but this will affect all

thermals

r

 

I should have mentioned this in my original post, but the GND polygon width

is 12 mils, and the isolate value is 10 mils.

I know that if I used a tRestrict wire to prevent the polygon from

automatically connecting to the GND pad of the resistor, then I can run a

trace between the polygon and the pad, but I was hoping for an automatic

way to do this.  I have to do this for 16 different circuits.

-Dave Pollum

Ing. J.M. Rafetseder wrote:

You can also change the width of the polygon, but this will affect all

thermals

r

 

 

or add a new polygon with same name and different rank and width

overlapping the too wide polygon. I am not sure if you have to modify

the thicker outline to be out of the way or rank may. I don't remember

if rank or's or and's with the same net name.

Paul R.

Dave P schrieb:

By "thermal ties" I mean the copper that connects a pad to a copper pour.

I have a situation with a 0805 chip resistor:

• the left pad is connected to an 8-mil trace coming into the pad and to an

8-mil trace exiting the pad.

• the right pad connects to the GND polygon, with 3 16~18-mil traces. 

So this means that there is a LOT more copper on the right end of the

resistor.  I have read that in this type of situation when the board is

reflow soldered that the part can get pulled over to one pad and make poor

connection to the other pad, or that the part can "tombstone".

To my knowledge, with 0805 parts the tombstone risk is not too high.

This is more critical with smaller part sizes (0603, 0402...).

If what

I've read is correct, how do I make the copper (thermal) ties on the right

pad, narrower?  I played with DRC/Supply values, with no success.

The width of the thermal ties is automatically calculated based on the

pad diameter/size, and then limited to twice the polygon width (this is

also described in the manual and help somewhere...).

If you want narrower ties, simply reduce the polygon width. Don't to

this excessively, since you'd get /huge/ plot files then - and angry

callbacks from your board house.

For our standard boards using 0.3 mm tracks, I use 0.15 mm polygons

which result in ties of exactly the common track width. Of course, in

your situation there are three ties against one track, but that has

never led to any problems here (we also use 0805 as standard size).

BTW, I'd gladly post a pic of a portion of my board, but I don't know how

to save a portion of the board as a graphic.  I use EAGLE v5.6.0 and Win

XP/sp3.

Export an image, then cutout the section. I can highly recommend

FastStone for this (very comfortable and efficient).

You could also take a partial screenshot. Again, FastStone is your very

comfortable friend.

<http://www.faststone.org/FSViewerDetail.htm>

Tilmann

On Wed, 01 Jul 2009 08:20:41 +0200, Tilmann Reh <user@domain.invalid>

wrote:

Dave P schrieb:

 

By "thermal ties" I mean the copper that connects a pad to a copper pour.

I have a situation with a 0805 chip resistor:

• the left pad is connected to an 8-mil trace coming into the pad and to an

8-mil trace exiting the pad.

• the right pad connects to the GND polygon, with 3 16~18-mil traces. 

So this means that there is a LOT more copper on the right end of the

resistor.  I have read that in this type of situation when the board is

reflow soldered that the part can get pulled over to one pad and make poor

connection to the other pad, or that the part can "tombstone".

 

To my knowledge, with 0805 parts the tombstone risk is not too high.

This is more critical with smaller part sizes (0603, 0402...).

Thanks for that info.

If what

I've read is correct, how do I make the copper (thermal) ties on the right

pad, narrower?  I played with DRC/Supply values, with no success.

 

The width of the thermal ties is automatically calculated based on the

pad diameter/size, and then limited to twice the polygon width (this is

also described in the manual and help somewhere...).

 

If you want narrower ties, simply reduce the polygon width. Don't to

this excessively, since you'd get /huge/ plot files then - and angry

callbacks from your board house.

 

For our standard boards using 0.3 mm tracks, I use 0.15 mm polygons

which result in ties of exactly the common track width. Of course, in

your situation there are three ties against one track, but that has

never led to any problems here (we also use 0805 as standard size).

OK, I will try narrower polygons.

BTW, I'd gladly post a pic of a portion of my board, but I don't know how

to save a portion of the board as a graphic.  I use EAGLE v5.6.0 and Win

XP/sp3.

 

Export an image, then cutout the section. I can highly recommend

FastStone for this (very comfortable and efficient).

 

You could also take a partial screenshot. Again, FastStone is your very

comfortable friend.

 

<http://www.faststone.org/FSViewerDetail.htm>

 

Tilmann

Thanks, Tilmann

-Dave Pollum