Preventing a trace with via from linking to plane

Am 02.09.2016 um 13:11 schrieb Steve Kale:

 

I have a board in which I have bypass caps filtering the supply to an op amp.  The "V-" of the op amp supply is GND and GND is a plane on an internal layer. However rather than just using a via to connect the low side of the bypass caps to the GND plane I'd like to force a routing to the via which connects the op amp V- pin to the GND plane. This would be straightforward except I need another via to make the routing on the top rather than bottom layer (where the op amp is sitting) and as soon as I place the via to get to the top layer it connects to the GND plane. How can I isolate this via from GND?

You can draw a wall of keepout around you via to prevent the GND to connect.

Just for my curiosity: why do you want to make such strange conntection?

Thorsten

I guess there is little difference given the use of a plane but the intention was more directly place the caps across the supply pins.

Steve Kale wrote:

 

This would be straightforward except I need another via to make the routing on the top rather than bottom layer (where the op amp is sitting)

Steve Kale wrote:

 

Btw I can only use vias that go through the entire board

So doesn't your via which connects to V- therefore go through the board so you can connect directly to it?

If you have a GND plane the lowest inductance solution for the decoupling capacitor is to place it as physically close to the V+ pin with a via right next to it to your V+ power plane and connect a via immediately at the other end of the cap to GND and then connect your V- to the GND plane with a via as close as possible to the V- pin. The placement and orientation of the cap should be such that it minimizes the overall distance. Your solution will increase the inductance in the loop a) because you are using a trace rather than the plane and b) because you are adding in an extra via, and the net result will be to reduce the effectiveness of the decoupling capacitor.

Best Regards,

Rachael

Steve Kale wrote:

 

This would be straightforward except I need another via to make the routing on the top rather than bottom layer (where the op amp is sitting)

Steve Kale wrote:

 

Btw I can only use vias that go through the entire board

So doesn't your via which connects to V- therefore go through the board so you can connect directly to it?

If you have a GND plane the lowest inductance solution for the decoupling capacitor is to place it as physically close to the V+ pin with a via right next to it to your V+ power plane and connect a via immediately at the other end of the cap to GND and then connect your V- to the GND plane with a via as close as possible to the V- pin. The placement and orientation of the cap should be such that it minimizes the overall distance. Your solution will increase the inductance in the loop a) because you are using a trace rather than the plane and b) because you are adding in an extra via, and the net result will be to reduce the effectiveness of the decoupling capacitor.

Best Regards,

Rachael

Take a look at page 6 of the link below. You are effectively doing what they show in the "incorrect" diagram.

http://www.analog.com/media/en/training-seminars/tutorials/MT-101.pdf

On 02.09.2016 14:32, rachaelp wrote:

Take a look at page 6 of the link below. You are effectively doing what they show in the "incorrect" diagram.

 

http://www.analog.com/media/en/training-seminars/tutorials/MT-101.pdf

Always interesting to discuss decoupling.. Whats religion and whats fact?

Yes the example has higher inductance on the track on top, but at the

same time, more via inductance between the cap and ic pad, but how wide

must this track be before you can define this as a local plane (or

perform better than the added via if you like)? If it became a low

(enough) inductance plane, would it not perform better than a 2 via

path? I guess you can simulate this.

You may also argue, since this may be a differential op-amp, maybe

common mode noise on v- and v+ would have better CMRR at the inputs?

Also, on the drawing I would turn the decoupling capacitor so its gnd

pad was pointing toward the ic gnd pad, again to reduce inductance.

Since they are nitpicking on the datasheet, why not continue? Maybe the

ic gnd pad via should be under the chip to reduce the current loop area

too, effectively making the current loop shaped like the number 8? That

would lower EMI.

My point is, the datasheets are not necessarily ideal. The tiny stuff

may be overkill, sometimes wrong, but it certainly doesnt harm to

improve the theory if done right.

Morten Leikvoll wrote on Fri, 02 September 2016 14:30

On 02.09.2016 14:32, rachaelp wrote:

Take a look at page 6 of the link below. You are effectively doing

what they show in the "incorrect" diagram.

 

 

http://www.analog.com/media/en/training-seminars/tutorials/MT-101.pdf

 

Always interesting to discuss decoupling.. Whats religion and whats

fact?

 

Yes the example has higher inductance on the track on top, but at the

same time, more via inductance between the cap and ic pad, but how wide

 

must this track be before you can define this as a local plane (or

perform better than the added via if you like)? If it became a low

(enough) inductance plane, would it not perform better than a 2 via

path? I guess you can simulate this.

 

You may also argue, since this may be a differential op-amp, maybe

common mode noise on v- and v+ would have better CMRR at the inputs?

 

Also, on the drawing I would turn the decoupling capacitor so its gnd

pad was pointing toward the ic gnd pad, again to reduce inductance.

 

Since they are nitpicking on the datasheet, why not continue? Maybe the

 

ic gnd pad via should be under the chip to reduce the current loop area

 

too, effectively making the current loop shaped like the number 8? That

 

would lower EMI.

 

My point is, the datasheets are not necessarily ideal. The tiny stuff

may be overkill, sometimes wrong, but it certainly doesnt harm to

improve the theory if done right.

Yes I agree, their example in the link I gave could have been improved by

turning the cap through 90 degrees. I'd actually said exactly that in the

previous post.

In the case of the OP's circuit I believe his cap is on the bottom and the

IC is on the top. That is minimum 2 vias to connect it up which is what my

solution had. The OP's solution would have 3 vias and a trace rather than a

plane, both of which would increase the inductance and reduce the

effectiveness of the decoupling.

You are right though, when it comes to decoupling there are a lot of myths

around and some people have some rather odd notions!

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

On 02/09/16 14:40, Rachael wrote:

You are right though, when it comes to decoupling there are a lot of myths

around and some people have some rather odd notions!

 

OK, so on that subject, what are people's opinions on the merits of

these two TQFP designs:

Example 1 is a 4-layer board, with a ground plane on an inner layer. The

cap is on the bottom of the board for an IC on the top.

Example 2 is a 2-layer board, reliant on flood fill for the ground

'plane'. The cap is on the top with the IC, its positive end as near as

possible to the power pin.

Thanks.  It seems I more or less have it "correct" at the moment but I was advised to 'connect the caps directly across the supply pins' which made me think I had it wrong. 

I did want to answer your question.  I can connect to the via to V- just fine.   I have the IC and decoupling caps on the same layer.  (Perhaps distances would be shorter if the decoupling caps were on the top layer directly above the op amp but space is limited.)  I have two instances of this on the board.  For one, the situation is easy as the decoupling caps can be oriented so their low side is very close to the V- via - I can connect both at the same via to GND.  For the other, I've found myself with the decoupling caps on the opposite side of the IC as the V- pin and routing on the same layer isn't possible.  Hence the contortion - if not a via to GND plane - of having to route from bottom to top layer with a via and then route across to the V- via to GND.  It's the first via (rather than the V- via) which posed the problem in Eagle.

I will examine placement again and stick to using vias to the GND plane.

Thanks

rachaelp wrote:

 

So doesn't your via which connects to V- therefore go through the board so you can connect directly to it?

 

If you have a GND plane the lowest inductance solution for the decoupling capacitor is to place it as physically close to the V+ pin with a via right next to it to your V+ power plane and connect a via immediately at the other end of the cap to GND and then connect your V- to the GND plane with a via as close as possible to the V- pin. The placement and orientation of the cap should be such that it minimizes the overall distance. Your solution will increase the inductance in the loop a) because you are using a trace rather than the plane and b) because you are adding in an extra via, and the net result will be to reduce the effectiveness of the decoupling capacitor.