Preventing a trace with via from linking to plane

Am 02.09.2016 um 13:11 schrieb Steve Kale:

 

I have a board in which I have bypass caps filtering the supply to an op amp.  The "V-" of the op amp supply is GND and GND is a plane on an internal layer. However rather than just using a via to connect the low side of the bypass caps to the GND plane I'd like to force a routing to the via which connects the op amp V- pin to the GND plane. This would be straightforward except I need another via to make the routing on the top rather than bottom layer (where the op amp is sitting) and as soon as I place the via to get to the top layer it connects to the GND plane. How can I isolate this via from GND?

You can draw a wall of keepout around you via to prevent the GND to connect.

Just for my curiosity: why do you want to make such strange conntection?

Thorsten

I guess there is little difference given the use of a plane but the intention was more directly place the caps across the supply pins.

Steve Kale wrote:

 

This would be straightforward except I need another via to make the routing on the top rather than bottom layer (where the op amp is sitting)

Steve Kale wrote:

 

Btw I can only use vias that go through the entire board

So doesn't your via which connects to V- therefore go through the board so you can connect directly to it?

If you have a GND plane the lowest inductance solution for the decoupling capacitor is to place it as physically close to the V+ pin with a via right next to it to your V+ power plane and connect a via immediately at the other end of the cap to GND and then connect your V- to the GND plane with a via as close as possible to the V- pin. The placement and orientation of the cap should be such that it minimizes the overall distance. Your solution will increase the inductance in the loop a) because you are using a trace rather than the plane and b) because you are adding in an extra via, and the net result will be to reduce the effectiveness of the decoupling capacitor.

Best Regards,

Rachael

Thanks.  It seems I more or less have it "correct" at the moment but I was advised to 'connect the caps directly across the supply pins' which made me think I had it wrong. 

I did want to answer your question.  I can connect to the via to V- just fine.   I have the IC and decoupling caps on the same layer.  (Perhaps distances would be shorter if the decoupling caps were on the top layer directly above the op amp but space is limited.)  I have two instances of this on the board.  For one, the situation is easy as the decoupling caps can be oriented so their low side is very close to the V- via - I can connect both at the same via to GND.  For the other, I've found myself with the decoupling caps on the opposite side of the IC as the V- pin and routing on the same layer isn't possible.  Hence the contortion - if not a via to GND plane - of having to route from bottom to top layer with a via and then route across to the V- via to GND.  It's the first via (rather than the V- via) which posed the problem in Eagle.

I will examine placement again and stick to using vias to the GND plane.

Thanks

rachaelp wrote:

 

So doesn't your via which connects to V- therefore go through the board so you can connect directly to it?

 

If you have a GND plane the lowest inductance solution for the decoupling capacitor is to place it as physically close to the V+ pin with a via right next to it to your V+ power plane and connect a via immediately at the other end of the cap to GND and then connect your V- to the GND plane with a via as close as possible to the V- pin. The placement and orientation of the cap should be such that it minimizes the overall distance. Your solution will increase the inductance in the loop a) because you are using a trace rather than the plane and b) because you are adding in an extra via, and the net result will be to reduce the effectiveness of the decoupling capacitor.

 

Thanks.  It seems I more or less have it "correct" at the moment but I was advised to 'connect the caps directly across the supply pins' which made me think I had it wrong. 

I did want to answer your question.  I can connect to the via to V- just fine.   I have the IC and decoupling caps on the same layer.  (Perhaps distances would be shorter if the decoupling caps were on the top layer directly above the op amp but space is limited.)  I have two instances of this on the board.  For one, the situation is easy as the decoupling caps can be oriented so their low side is very close to the V- via - I can connect both at the same via to GND.  For the other, I've found myself with the decoupling caps on the opposite side of the IC as the V- pin and routing on the same layer isn't possible.  Hence the contortion - if not a via to GND plane - of having to route from bottom to top layer with a via and then route across to the V- via to GND.  It's the first via (rather than the V- via) which posed the problem in Eagle.

I will examine placement again and stick to using vias to the GND plane.

Thanks

rachaelp wrote:

 

So doesn't your via which connects to V- therefore go through the board so you can connect directly to it?

 

If you have a GND plane the lowest inductance solution for the decoupling capacitor is to place it as physically close to the V+ pin with a via right next to it to your V+ power plane and connect a via immediately at the other end of the cap to GND and then connect your V- to the GND plane with a via as close as possible to the V- pin. The placement and orientation of the cap should be such that it minimizes the overall distance. Your solution will increase the inductance in the loop a) because you are using a trace rather than the plane and b) because you are adding in an extra via, and the net result will be to reduce the effectiveness of the decoupling capacitor.