I would like to have my THole pads with a pull back of 3mils and the vias tented by -1mil. I can't see any way this can be done
as vias don't come up in the selections. You can It select each via and do it but that's crazy.
Does anyone know how to do this?
For anything other than a simple PCB it may be difficult to have much control of SM expansion on vias. In CS this works in a crippled manner as compare to Altium Designer.
It looks to me like the options provided by CS aren't up to professional level control.
There should be three ways I know of, two mentioned above.
1) You can select them with the filter tool. First Reset Filter to get rid of any past filters. Then mouse pick View > Filter then choose groups <All> and Objects Via with Layers <All>. Then only the vias should be chosen. Use the mouse to drag a highlight box around them or press CTRL-A to pick them all. Then View > Object Inspector gets you to the PCB Inspector tab. There is a checkbox selection ofr Solder Mask Override but there seems to be no value to set so it isn't clear to me what the check box does. Tenting check boxes seem to work though. Some fabricators do not want to tent vias both sides as this can trap chemicals.
If you have different size vias it may be difficult to sort them this way. In AD you can use advance filters to get specific ones by size.
2) Preferred (if it worked): use rules (as mentioned) to define the mask for specific objects. Use Home > Design Rules
Pick Solder Mask Expansion as the rule category. In my CS the default was 0 for all pads. I typically prefer a default of 4mil (or 0.102mm) and make this smaller for high density parts (maybe as low as 2mm) or make it negative for solder mask defined pads or to encroach vias.
Look up an Altium tutorial video on how rules work. The basics are to right click on the rule category and pick New Rule (or left click on New Rule).
Rename your rule to something (e.g. SMExpand_Vias). However, I notice that there are limitations to the selection criteria in CS so it doesn't seem possible to match the object to specific hole sizes or as vias only.
3) Painstakingly, select each via and edit its properties. As the OP mentioned, this is crazy to do.
Perhaps a fourth way to handle via encroachment might be to tent both sides of the PCB for vias and then add a fabrication note that all tented vias larger than than 10mil (or so) do not need to plugged and those smaller can be encroached to prevent entrapment of chemicals. With a proper note the fabricators should be able to do it with their tools.
Maybe someone with fabrication knowledge can comment on better wording?
It seems like this is a case where anything sophisticated is a problem in CS.
If you know someone with Altium Designer it might be worth trying to have them export a rule and then try to import it into CS.
