polygon region short circuit

As Shabaz said, DRC errors should not be ignored unless the reason is known and acknowledged. Which layers of your PCB have polygons on them and which nets are they connected to?

Having 2 overlapping polygons on the same layer with different nets is generally a "no no". If you have to have polygons on the same layer with different nets, they shouldn't be overlapping.

Overlapping polygons is not a problem because when they are poured, they follow the design rules. My guess is that you need to repour the polygons.

I think this might be an error with circuit studio. As when i move the copper plane away like this the drc errors go away (you can see the polygons are still overlapping on other parts of the pcb and i get no DRC error). However when i move that copper polygon (which is connected to ground) back over J1 the errors come back for pin 3 (no connect) and pin 1 (12V).

The trace indicated by the orange arrow is on a mechanical layer and shouldn't interact with the Short circuit part of the DRC. It's meant for the design stage and shouldn't show up in the gerbers. the light gray area is a multi-layer pad, meaning it's a pad on the top, inner, and bottom layers. The red pad is a *hopefully plated slot. The silkscreen is the lighted traces on the footprint. That being said, exporting a gerber file and opening it up in a separate viewer like Gerbview would be a good idea at this point.

The DRC errors points to pads 1 & 3, apparently the GND polygon is touching those pads.

acw210ee try closing CS, opening again, repour all the polygons, run DRC again.

i looked at those traces and those are on the "top overlay" in the pcb footprint. whats interesting is i get no error for pin 5 when i do the drc only pins 1 and 3

^ I second this.

I've also had a buggy install of CS before. If the gerber files look good, and all else fails, it might not hurt to uninstall and reinstall it.

You can try putting a polygon pour cutout in the same area of those pads and see if the DRC error goes away.

Re-opening did not fix the issue. I was able to fix it by messing around with the design rules. It seems it has an issue routing polygons around slot shaped pins. Essentially in design rules, electrical, clearance, i changed the polygon minimum clearances to 10 mils for everything. Repoured the polygons, then changed the design rules back to 6 mils, then did not repour the polygons and did a DRC check. That removed the short circuit errors, however i still have 3 clearance errors. 

it is where that 6 mil white mark is, there is nothing there to even be "clear" of so it makes no sense so I am going to ignore it. Overall i think the root cause is circuitstudio has some issues with the design rules when pouring polygons around slot shaped pads. 

It's always been fine for me.

Can you go under "view", select "single layer mode", and take screenshots of the same area on each copper layer? It might be referring to something on a different layer.

layers are bot, signal 1, signal 2, top

layers are bot, signal 1, signal 2, top

It could be worth trying a clearance of (say) 6.1 mil, just in case there is more than one parameter set to the same value, and rounding error on a curve or similar causing some weird issue. For instance with EAGLE, I seem to recall the polygons would be drawn with a line width too, and it was occasionally possible for rounding issues to cause errors if multiple rules used the same value. 

It looks like you're doing everything right. I think the software is just running into some sort of bug. As long as you check the gerbers after you export them, you can probably ignore it.

That being said, if you still want to get your DRC to pass, you could try to do some experiments like adding a different through-hole component to that area of the PCB, and seeing if the issue pops up on that one too. If it doesn't you could just try to remake the component and footprint yourself from scratch.

I agree, everything points to a software bug. I think putting a polygon pour cutout on those pads should avoid the DRC errors.