ANP007 // ROBERT SCHILLINGER // DR. RICHARD BLAKEY
The USB connector and standard are one of the most widely implemented and successful interfaces ever used. The applications are commercial and industrial, and both have been pushing the standard to be faster. The USB standard has been updated to version 3.1. This standard increases data transfer speeds to 5 GBits/s (Gen 1) and 10 GBit/s (Gen 2). Higher data transfer speeds are required due to the ever-increasing resolution of media and network data rate requirements.
Increasing the data transfer speed means important parameters need to be considered, as this has implications in data transmission lines. Attenuating unwanted signals while maintaining the speed and integrity of data transfer is of paramount importance for EMI compatibility. For high-speed data lines, Würth Elektronik has common mode chokes for EMI suppression and TVS diodes for ESD protection. The WE-CNSW HF has been developed to attenuate common mode noise signals while maintaining signal integrity up to 10 GBit/s. For ESD protection, the WE-TVS is available with very low capacitances (< 0.6 pF) and is the ideal choice for higher frequencies. These components are also well suited for other high data transfer interfaces such as HDMI 4K, DisplayPort or GBit LAN.
This application note outlines the components needed to protect USB 3.1 devices and attenuate EMI that may cause the device to fail EMC testing. This will be demonstrated in USB Type-C dongle (Figure 1) to characterize the effectiveness of the components. For information and components suitable for USB 2.0, please refer to:
Figure 1: USB-C dongle used to demonstrate USB 3.1 filtering and protection
2 EMC considerations of symmetrical data lines
The USB interface is a bidirectional, symmetric interface (Figure 2).
Figure 2: The USB interface is symmetrical and bidirectional
Figure 3: The symmetrical interface with its measurable interference voltages
VDM, interference voltage between the signal wires, and VCM, interference voltage between the voltage midpoint and the reference voltage (ground, cable shield), are both measurable. This means that both differential mode and common mode interference voltages can affect the USB transmission path. This can be interference from the interface itself or an electromagnetic effect from the environment in the form of inductive, capacitive or wave coupling.
In the case of USB transmission, differential mode interference is mainly generated by non-linear signal harmonics due to impedance mismatching and inadequate circuit design. Asymmetry of the transmission path (e.g. transmitter, circuit board traces, conductor tracks, filters or cables) can lead to interference radiation and impairment of signal quality.
Common mode interference arises from parasitic coupling in the circuit environment of the USB controller. This is usually due to capacitive coupling on the USB signal with rising interference frequency and increasing amplitude. However, these interference types are found on both USB wires in phase and at the same amplitude and therefore the effect on the intended signal is reduced. Asymmetries in the cable or at the receiver often convert the originally common mode into a differential mode interference signal, however, which can then contribute to signal impairment (Figure 4).
Figure 4: Conversion of differential mode to common mode interference due to parasitic coupling capacitances in the one channel of a differential pair
Differential mode data transmission offers a significant advantage over the simple coaxial cable when it comes to the effect of interference on the USB. Depending on the shielding effectiveness of a coaxial cable, a transient, from a parallel mains cable for example, couples into the data line and interferes with the data signal (Figure 5). This leads to data or communication errors, which depend on the interference signal length and amplitude.
Symmetrical transmission techniques have numerous advantages including lower interference emission and higher interference immunity (Figure 3).
Figure 5: Effect of interference on a coaxial data transmission path
Figure 6 represents the case of differential mode data transmission with twisted pair wires. The polarity of the intended signal is reversed so that equal but opposite signals propagate. The signal difference is evaluated at the input of the receiver. The interference signal affects both wires in the same phase, so this cannot have an effect as an interference signal at the receiver.
Furthermore, in the case of the inductive interference effect (magnetic field), the twisting of the wires achieves compensation of the interference effect. Because of the symmetry of the partial inductances of the respective twisted wire, the interference influences compensate each other.
Figure 6: Compensation of electrical interference coupling of the differential mode signal input and twisted wire pairs
2.3.Possibilities of reducing emission and increasing interference immunity
It is apparent in practice that interference emissions cannot be completely prevented and, therefore, interference immunity has stringent requirements. The reason lies in many details, of which these are the most important:
- The inputs/outputs of the USB controller are insufficiently symmetrical; the USB signal displays common mode interference.
- The layout is not HF/EMC compatible, parasitic capacitances and the lack of wave impedance matching generate common mode interference.
- The circuit design (USB filter) is inadequate, the filters affect the signal quality and/or the insertion loss is too low.
- The interface design (receptacle, housing) is inadequate, poor ground reduces the shield attenuation of the cable, filters have poor ground reference.
- The USB cable is asymmetrical, poorly shielded, has inadequate ground connection. The cable deteriorates the signal quality, radiates signal harmonics and has insufficient shield attenuation towards external interference sources.
2.4.Methods of reducing emission and increasing interference immunity
Common mode chokes (CMC) are fundamental for attenuating interference. Extremely low capacitances between the data line and ground are needed with USB 3.1. The values are strongly dependent on the properties of the CMC. The CMC must have a high degree of symmetry and low stray capacitance between the two windings. Furthermore, the ferrite permeability must have a low real part in the data signal frequency range, in order to reduce unwanted reflections at the CMC. The imaginary part of the permeability should be high within the frequency range to be filtered.
Transient interference signals, such as ESD and bursts, can generally be limited with varistors. Especially SMD multilayer varistors, which are particularly fast and withstand a high level of energy. However, their capacitance is generally too high, possibly corrupting the signal and definitely making them unsuitable for limiting transients in USB 3.1 data lines. Transient limitation with diodes is shown in Figure 7. Transients are limited against ground, both on D+ as well as on D- up to the forward voltage UF of the diodes. This voltage is around 0.7 V for silicon diodes. A problem appears very quickly here, which is why the diode pair bellow has two red flashes: The signal voltage of the "mid-speed" signal is up to 2.8 V (D+ to D-), i.e. 1.4 V to ground. The positive branch must therefore be provided with an "offset" in order to avoid impairing higher signal voltages.
Figure 7: Diode array to reduce coupled transients (burst, ESD) on the USB interface
An additional TVS diode with a limitation voltage of 6 V sets the threshold value to approximately 6.7 V. This is sufficient protection, as TVS diodes with lower limitation voltages are too slow to limit ESD. The voltage levels are illustrated in Figure 9. Transient limitation at the connection of the supply voltage can be achieved at the same time using the additional diode D5 in Figure 8. Although the capacitance of the TVS diode is low at 5 pF, it would be too high for USB 3.1. As VR1 is in series with D3 and D4, however, the capacitance of VR1 reduces the overall capacitance that affects the signal, as D3 and D4 have capacitances of approximately 2 pF. The capacitors are in series with D3 and D4 with reference to the signal, there is an overall signal-to-signal capacitive load of 2 pF and signal against ground of around 3 pF.
Figure 8: Diode array to reduce coupled transients (burst, ESD) on the USB interface with "offset" for higher signal levels
Figure 9: Voltage levels of the positive diode path
For the supply voltage, a low-pass π-filter with two ceramic capacitors and an inductor can be used (Figure 10). The current carrying capability is an important parameter, which is specified in the datasheets. The components should be selected to be adequate for the respective power output.
Figure 10: π-filter topology
3 High frequency common mode chokes
Common mode chokes are inductors with two or more isolated windings. When a common mode signal passes through the component, magnetic flux accumulates in the core, resulting in high impedance at some frequencies. As differential signals cancel out the magnetic flux in the core, the impedance is low, allowing the signal to pass nearly un-attenuated.
Figure 11: WE-CNSW HF
Figure 12: Eye diagram with the WE-CNSW filter (left) and the WE-CNSW HF filter (right) at 5 GBit/s
Figure 13: Eye diagram with the WE-CNSW filter (left) and the WE-CNSW HF filter (right) at 2.5 GBit/s
In Figure 12, the eye diagram for the WE‑CNSW (left side) and the WE‑CNSW HF (right side) is compared at 5 GBit/s. Both components have almost the same impedance in common mode (Figure 15). The main difference is in the differential mode impedance. The difference is big enough to see that the eye is smaller with the standard version.
At 2.5 GBit/s the difference is smaller (Figure 13). The harmonics of the signal are not filtered by the high frequency component nor the standard component.
The difference between the WE‑CNSW and the WE‑CNSW HF is not significant in the low frequency data range. Both will allow the data signal to pass as both WE‑CNSW series are designed to have low differential impedance in this frequency range. However, a data signal with a higher frequency will be presented with higher levels of differential impedance. With the WE‑CNSW, the cut-off frequency is about 2 GHz, whereas with the WE‑CNSW HF the cut-off frequency is much higher, while still having the same impedance for common mode signals. At a data rate of 7 GBit/s the WE‑CNSW also attenuates the base frequency of the signal while the WE‑CNSW HF only attenuates the high frequency harmonics resulting in a passed eye diagram test (Figure 14).
4 Transient voltage suppression (TVS) diodes
Due to their construction, modern semiconductors are fabricated with extremely small tolerance to high voltages. Integrated ESD protection normally works up to 500 V, but higher tolerance is needed in most applications to ensure stable and long-term functionality.
Figure 14: Eye diagram with the WE-CNSW filter (left) and the WE-CNSW HF filter (right) at 7 GBit/s
Figure 16: WE-TVS Super Speed Series
Würth Elektronik has launched the high frequency TVS diodes array series called WE-TVS Super Speed Series. These TVS diode arrays protect against ESD pulses according to EN 61000-4-2. Due to their ultra-low capacitance (< 0.6 pF) they are nearly invisible to high bit rate data such as USB 3.1, HDMI 2.0 and GBit Ethernet.
Additionally, the WE-TVS High Speed Series are high performance TVS diode arrays that include surge rated diodes. They are an excellent choice to protect high-speed data lines, like USB 2.0, VGA and Ethernet. The WE-TVS High Speed Series exceeds the requirements outlined in EN 61000-4-2. Due to their ultra-low capacitance (< 2.0 pF) they are nearly invisible on the signal lines.
Modern demands have been pushing for a universal bus (USB) to be smaller, thinner and lighter. The USB Type-C connector was developed in parallel with the USB 3.1 standard (SuperSpeed+, USB 3.1 Gen 2), which is the updated standard of USB 3.0 (now USB 3.1 Gen 1). The connector now includes 24 pins (Figure 13) which include four power/ground pairs, two differential pairs (non-SuperSpeed+) and four SuperSpeed+ pairs (two used for USB 3.1). USB Type-C has data rates of up to 10 Gbit/s using one SuperSpeed+ and two SuperSpeed line pairs and can carry up to 5 A (100 W). To maintain signal integrity at these speeds, the capacitance of ESD devices must be even lower than that for USB 2.0 while CMCs need to present impedance to differential mode noise at higher frequencies.
Figure 18: USB Type-C pin layout
From the above pin layout, the power pairs are A1/A4, A9/A12, B1/B4 and B9/B12, the SuperSpeed+ pairs A2/A3/B10/B11 and A10/A11/B2/B3 and the non-SuperSpeed+ A6/A7 and B6/B7. These three functions can be treated separately and the necessary protection and filtering can be seen below (Figure 19).
Figure 19: Block diagram of the USB Type-C dongle
Additionally, A5/B5 are used to detect the connection and configure the interface. A8/B8 can be used for audio or additional features that have yet to be designated.
The nominal differential impedance of USB 3.1 data lines is 90 Ω, which must be maintained in the differential microstrip of the dongle. Z0 is calculated using the standard microstrip formula (1). To achieve impedance matching, the trace width w and height t, the trace separation distance s of the differential data traces in addition to the PCB permittivity and thickness h must be considered (Equation 2).
The calculated parameters were implemented as seen below (Figure 20).
Figure 21: Visualization of the USB dongle
5.1.USB 3.1 power channels
As previously stated, the power bus of the USB Type-C connector can handle up to 100 W (20 V / 5 A) when the cable is rated to such power. However, most applications will not use this high power capability. Therefore, the power bus filter must be designed to tolerate the power to be used by the application.
The USB 3.1 standard states a data rate of to 5 GBits/s (Gen 1) and 10 GBit/s (Gen 2). To attenuate any high frequency noise coupling to the power line, a low pass filter can be used with a cut-off frequency of approximately 1/10th of the data rate.
5.2.100 W (20 V / 5 A) applications
Figure 22: Complex impedance curve and the effect of DC current on the impedance of the WE-MPSB SMD ferrite (742 792 261 01)
The WE-MSPB (742 792 261 01) ferrite has its maximum impedance in the range from approximately 100 MHz to 1000 MHz in which the highest level of interference is to be anticipated in USB data transmission. At 750 MHz the ferrite acts like an ohmic resistor with no reactive components. Above this resonance frequency, the capacitive behavior dominates the impedance. Table 1 shows an overview of the most important parameters, the impedance curve is presented in Figure 22.
± 25 %
ΔT = 40 K
Table 1: Electrical data of WE-MPSB SMD ferrite (742 792 261 01)
1±0.2 VRMS; 1 kHz ± 10 %
± 20 %
1±0.2 VRMS; 1 kHz ± 10 %
≤ 10 %
Apply UR for 120 s max
≥ 0.02 GΩ
Table 2: WCAP-CSGP (885 012 107 018) electrical characteristics
Additionally, a filter is required to bypass any additional high frequency noise. A π-filter was chosen as they have a high insertion loss because both the source and the sink in the power supply are of low impedance. This gives rise to an optimal mismatch and therefore maximum suppression. The following filter was implemented using well-known filter equations.
Figure 23: Implemented SMD ferrites, π-filter and TVS diode topology for 100 W power capability
Table 3: Selected components for the 100 W design
5.3.60 W (20 V / 3 A) Applications
As a specialized cable is needed to handle 100 W of power, most applications will use 60 W or lower, which is the highest rated power of a ‘normal’ cable. Therefore, it may not be necessary to implement a filter that can handle 100 W. The following filter is implemented in a similar way to the 100 W filter but uses components with lower current handling capability and therefore, a more compact design.
Table 4: Selected components for the 60 W design
Figure 24: Simulated attenuation of the power line filter rated for 60 W and 100 W in comparison
5.4.USB 3.1 SuperSpeed+ channels
The WE-CNSW HF (744 233 56 00) is the heart of the data line filter. On account of its winding technology, the WE-CNSW HF has a high degree of symmetry and low parasitic capacitances. The structure is shown in Figure 25 and the most important parameters are given in Table 5.
± 25 %
ΔT = 20 K
T = 20 °C
Table 5: Electrical characteristics of the current-compensated choke (744 233 56 00)
Figure 25: WE-CNSW HF (744 233 56 00) for the data line filter
The impedance curve and insertion loss of the CMC in common and differential mode is presented in Figure 26. Common mode noise occurs when the same interference components propagate in the same direction on the positive and negative channels with respect to ground. This is always the case for capacitive or inductive coupling on the circuit or its conductor tracks. Therefore, this impedance component must be as high as possible. At 100 MHz the CMC has around 60 Ω. The differential mode impedance occurs due to the stray inductance of the winding structure. This impedance must be as small as possible at the data frequency.
Figure 26: Impedance curve and insertion loss of WE-CNSW HF @ 50 Ω (744 233 56 00)
Including capacitance in the filter forms a low-pass second order filter. A diode array is used here instead of capacitors. The integrated diodes also have a parasitic capacitance, which can be effectively used. In addition, the parasitic inductance of the TVS diodes in the array is very low. This is necessary to attain a short response time to the overvoltage transients. Therefore, an almost ideal capacitor is combined with effective transient protection. The most important electrical characteristics and the structure of the array are presented in Table 6 and Figure 27.
VGND = 0 V; VI/O = 1.65 V; f = 1 MHz; I/O to GND
VGND = 0 V; VI/O = 1.65 V; f = 1 MHz; I/O to I/O
Table 6: Electrical characteristics of the WE-TVS Super Speed Series (824 012 823)
Figure 27: Electrical schematic and structure of the diode array WE-TVS (824 012 823)
The circuit board with its conductor tracks is an arrangement of components with capacitances and inductances. The layout therefore has to be designed according to the circuit requirements. A simple LC low-pass filter can be significantly impaired in its effectiveness by an unfavorable layout (Figure 28).
Figure 28: Example of a low-pass filter for high frequencies with an unfavorable layout
There are a number of issues with the above layout, which include:
- The ground connection to the capacitor is too long. 1 cm of track corresponds to 6-10 nH inductance.
- The ground connection should pass directly to the housing, as the ground reference of the cable shielding and the ground reference of the filter must lie on the same HF potential.
- A stub line to the capacitor passes between the inductor and capacitor. This stub line is an additional inductance in series with the capacitor and, as a result of the higher reactance of the inductance with increasing frequency, renders the capacitor ineffective.
- The filter input and filter output couple inductively with each other. The filter is short-circuited with increasing frequencies.
- The components couple capacitively as they are located parallel to one other. Here too, the coupling is greater with increasing frequency.
The corrected layout with the associated HF-compatible arrangement is shown in Figure 29.
Figure 29: HF-optimized layout of an LC filter
This layout is better as:
- The contraction prevents interference current is bypassed at the capacitor. The capacitor "lies" in the signal path.
- The perpendicular arrangement of the components prevents mutual coupling.
- The short ground connection at the capacitor, which is of low impedance as a result of two through-contacts, offers an ideal high frequency reference point for the capacitor.
Figure 30: Eye diagram of the dongle with activated USB equalizer (@ 10 GBit/s)
Measurement setup for measuring the connection quality with 1 m cable and associated eye diagram at 5 GBit/s (USB 3.1 Gen 1). The structure serves as the basis for subsequent measurements with the Type C dongle. Figure 32 shows the differential impedance Zdiff in a time domain representation, which corresponds to a distance from the reference plane on the left side (male connector). As components are added to the PCB, the effect on the signal can be observed. The first measurement was conducted with an unpopulated PCB. The second includes the CMC, the third the TVS diodes and the last shows the effect when the solder mask is applied. The basis is the adapter with all components and solder resist included. The receiver can open the eye again with the USB equalizer settings based upon the USB 3.1 r1.0 specification. With optimized components, you can achieve better results in advance and thus increase the range. The eye pattern test shows that the WE-TVS and WE-CNSW HF do not disturb the USB 3.1 signal. To refresh the signal, there is an equalizer in each USB receiver, which is responsible for opening the eye (Figure 30)
6 Interface design kit
Figure 31: Time domain measurements and eye diagram of USB Type-C dongle
To facilitate the design of interfaces, Würth Elektronik has launched a dedicated Interface Design Kit (744 999). This design kit includes a design guide for USB 2.0 to USB 3.1, HDMI, CAN, Ethernet (100 and
1000 Base-T), VGA, DVI, RS232, RS485 interfaces and all the components used. These are ESD suppressors, SMD common mode
chokes, chip bead ferrites, LAN transformers and the corresponding connectors. The color scheme makes it easy to locate the suitable parts for your application. Just follow the specific application color and select the suitable parts. For each application, there is a simple block schematic, which shows how to place the different components to get the best result.
Figure 32: Time domain measurements and eye diagram of USB Type-C dongle
- 1. Bill of Material (BOM)
WE Order Code
|Farnell Order Code|
C1 / C2
C = 4.7 µF (25 V)
D1 / D2 / D3 / D4
WE-TVS Super Speed TVS Diode Array,
VDC = 3,3 V; IPeak = 3 A;
WE-TVS Super Speed TVS Diode Array,
VDC = 5 V; IPeak = 5 A;
WE-TVS Standard Speed TVS Diode, Unidir, ESD Protection
VDC = 20 V; IPeak = 24 A;
L = 90 Ω @ 100 MHz
L2 / L3 / L3 / L4
L = 60 Ω @ 100 MHz
L6 / L8
L = 100 Ω @ 100 MHz, IR = 8 A, ESR = 6 mΩ
L = 1.2 µH, IR ‘= 5.8 A
R1 / R2
R = 2.2 kΩ
WR-COM; Male USB 3.1 Type C 24 pins 90° THT & SMT LP 0.8
WR-COM Female USB 3.1 Type C 24 pins 90° THT & SMT LP 1.0
The Application Note is based on our knowledge and experience of typical requirements concerning these areas. It serves as general guidance and should not be construed as a commitment for the suitability for customer applications by Würth Elektronik eiSos GmbH & Co. KG. The information in the Application Note is subject to change without notice. This document and parts thereof must not be reproduced or copied without written permission, and contents thereof must not be imparted to a third party nor be used for any unauthorized purpose.
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