Raspberry Pi - Hardware Flaws and Fixups?

Now that people have actually started receiving the boards so the design in final, is the schematic close to being posted?  I looked around again in various likely places just now, but haven't spotted it yet.

actually, the design may not be quite final yet.  Liz said: "Happily, we’ve found it doesn’t need a shielded enclosure to reach Class B, although it will require a (very minimal) redesign." http://www.raspberrypi.org/archives/978, page 3, April 10, 2012 at 7:04 pm.

It hasn't been announced when such a change might be implemented, but probably better sooner rather than later, given the large production runs planned, perhaps along with a change to fix the SD card voltage issue.

Hi Chris,

I've gotten I2C working now from the commandline "bitibanging" utility. I was just browsing around on the forum to find a place where I can post a link to the software. :-)

Which reminds me: I don't have I2C read implemented yet....[time passes] .... OK. Done! :-)

Here are the commandline utilities to control GPIO, SPI and I2C.

http://www.bitwizard.nl/software/gpio_spi_i2c_20120419.tgz

Some sample scripts are included to make it easy to work with my I2c and SPI boards.

I'll start looking into writing the I2C and SPI kernel drivers shortly.

It could very well be that I decide that what I want from a kernel driver is not what the standard I2C and SPI kernel drivers do. I want to be able to easily, from userspace, interact with the devices on the bus. Eventually it should be something like:

echo 1 > /dev/motor

and the motor starts turning. :-)

OT: Chris, your name sounds familiar. Were you involved with Linux in the early years? Google shows that there is an actor with your name too. (or is that you?) :-)

Great work Roger! I've emailed you via the bitwizard site.

There are a few Chris Evans's about. I'm new to Linux!

Ha, I already wondered how long it would take you, to show something like this....

I think it is a good picture for the frontpage on raspberrypi.org....

Can you perhaps measure the pcb for me. I am getting different answers from people.

Best guess now is  85.0 x 56.0   or  85.0 x 56.2

Hans

Observation about USB power supplies: not sure if relevant to RasPi or not.

I was making some load measurements on a bunch of 5V USB power supplies here, unrelated to RasPi stuff. Got some confusing results, until I realized something I didn't know: some of those cable-less "wall wart" USB power supplies with just a USB jack, connect the internal ground pin (cable black wire) to the connector shield (cable braid), and some do not. So in some cases you'll have the ground return current flowing on the shield (if your device connects ground and shield) and in some cases, not. In case of interest.

Thanks for all the info Pete. A summary of possible 'minor' hardware changes that I've spotted in the forums:

1. I2S implement  as per the data sheet

2. SD card voltage option bank change, as per Dom's posting in: http://www.raspberrypi.org/forum/general-discussion/where-is-the-bottleneck#p62401

3. USB OTG Id Pin to spare GPIO pin (effective only on Model A) as per:

http://www.raspberrypi.org/forum/features-and-requests/cheap-but-crucial-model-a-feature-request-read-this?value=gpio%20usb%20pin%20request&type=2&include=1&search=1&ret=all

I'm not sure if the next two are technically possible!

4. Assisting POE (spare wires variant) adaptors exist that inject power onto the unused lines of ethernet and then split them out again after a cable

run see: http://www.cjemicros.co.uk/micros/individual/newprodpages/prodinfo.php?prodcode=4D-RPI-POE-IS-C (The Raspberry Pi adaptor cables doubles the price!) but if R-Pi's RJ45 could be changed for a variant that took the extra lines Earth to R-Pi's Earth and the Injected Power lines to R-Pi 5V via a link.

Pros: simple for end users to setup and injector only cable should be cheap.

Cons: POE variant of RJ45 with magnetics needed [1], cost, Reduced Isolation and extra link needed.

5. Assisting POE (via GPIO daughter board) If a POE daughter board was plugged into the GPIO pins with the daughter board having a POE input

RJ45 on it, supplying power to the R-Pi. The four ethernet data line output from the daughter board being connected to currently unused GPIO pins. I suspect inputting ethernet via the GPIO pins breaks various rules and could add to RF output:-(

Original suggestion at: http://www.raspberrypi.org/forum/features-and-requests/routing-ethernet-pins-4578-to-the-expansion-port

[1] I found a mag jack that might the type needed at: http://www.adam-tech.com/catalog/2012/page_009-049.pdf

See page 37 of 41 (marked Page 45) layout M16

n.b. I'm intrigued, what do the two diodes on the underside near the USB sockets protect?

I'd thought the USB ports, but people have mentioned on the forums that they have (unreliably) powered R-Pis via one of the two USB ports.

mmm, I really hope those "power issues" turn out to be just bad cable/adaptors/ppl doing it wrong.

You guys are working on it I suppose.

btw PeteL, what is requiring redesign (for full compliance)? That's what is bugging me, since it leads to another question: when will this be implemented (and then re-certified)? Before or after the queue of orders?

I guess "what are the changes needed" is more your cup of coffee (or better tea), so that's what I'd really like you to enlight me on.

Btw, is it just me or those 2k units feel a lot like a pre-serie?

"those 2K" should be "those 10k". The other 8k are Guaranteed to be exactly the same: they were produced feb-march just like the first 2k that are delivered right now.

and yes, I too would want to know what changes seem to be neccessary and when they will go through.

What is the HD interface? (schematics P4 left top)

What value is typical for the built-in pullup/pulldown? I expect that to be on the order of 50-100k. In that case you can encode 3^4 different board revisions with the 4 board-revision strap resistors:

read value. If zero, enable pullup, if one enable pulldown. If value now changes, the strap is left "open", so that's the third value.  (Ah! found them!).

There is an error in the schematics. p3 mentions the "USB" part of the LAN9512 as "model A only". That should be "Model B only" of course.

R22-R25, R28, C28 are missing their "Model B only" tag.

Why is there a line going from R25 to R22?

Due to space constraints the 100M led is labeled 10M on the board. How about calling that "FE" for "Fast Ethernet"? That's what 100M was called back in the days.

On the other hand, I would much rather have a BCM2835 GPIO pin control a led in that position. If we want, we can program it for the 100M/FE function in software, but it provides those who are going "bare bones" with an extra debugging option.

Similarly, the FDX led is nowadays a bit outdated. Why on earth are we still interested in that statusbit? Any reasonably recent setup will run full duplex, and it won't help in debugging in seeing that led remain off. Again: A gpio LED would be a nice replacement. The easiest way to notice a halff duplex link is to watch "dmesg": smsc95xx 1-1.1:1.0: eth0: link up, 100Mbps, full-duplex, lpa 0xC5E1

What is the purpose of D15, D16? I'm thinking: Protection against static discharges, right? The question is: Wouldn't it be better to connect their kathode to +5V0 instead of +5V0_HDMI? The +5V_HDMI is just a small net that only has the 100N C75 on it....

Are the HDMI_SDA and HDMI_SCL pins 5V tolerant? I wouldn't have guessed.

On the other hand, I would much rather have a BCM2835 GPIO pin control a led in that position. If we want, we can program it for the 100M/FE function in software, but it provides those who are going "bare bones" with an extra debugging option.

 

Similarly, the FDX led is nowadays a bit outdated. Why on earth are we still interested in that statusbit? Any reasonably recent setup will run full duplex, and it won't help in debugging in seeing that led remain off. Again: A gpio LED would be a nice replacement. The easiest way to notice a halff duplex link is to watch "dmesg": smsc95xx 1-1.1:1.0: eth0: link up, 100Mbps,full-duplex, lpa 0xC5E1

I agree with that, FDX led is not really usefull, it would be much better if that could be used as a gpio led.

That way you can directly let kids program the led without the need for extra hardware.

Hans

Well, in principle you can use the FDX as a GPIO LED.  The difficulty is that you need to talk to the LAN9512 in USB-speak to configure and toggle it, and the driver may make this difficult.  Still, students would learn a lot about USB drivers trying to do it :-)

Was it here that someone asked me to measure the physical size of the 'pi? Mine is 55.9 x 84.9mm.

Was it here that someone asked me to measure the physical size of the 'pi? Mine is 55.9 x 84.9mm.

Yes me...  thx Roger.

Hans

I know it is only slightly different, and may not matter at all, but in a post on the Raspberrypi.org website one recipient (another case manufacturer actually) has said that: The board is 85.00 x 56.17

Hi David, yes I know   ModMyPi measured that....  That is why I asked Roger... I know he is very precise...

So probably the pcb board is 85.0 x 56.0  with 0.2 tolerance

All my cases are made 85.6 x 56.0, and I have 4 lying here waiting.... but I was not that lucky in getting a Pi...

So the pcb will fit,  even if it is .17 wider I can probably shave a little off the pcb board...

Hans

The schematic doesn't appear to show the memory chip-select lines,

but Gert has mentioned that the SoC has only a single chip-select line,

which prevents stacking more than one memory chip, as described here:

http://www.engadget.com/2011/03/25/samsung-starts-baking-30nm-4gb-lpddr2-chips-packaging-2gb-mobil/

Are the production volumes large enough now that Broadcom might consider

presumably minor changes such as adding an additional chip-select line?

The schematic does not show any of the connections to the Package on Package (POP) memory that actually sits on top of the BCM2835.  It never gets to the PCB so there is just a hidden attribute that calls up the part onto the parts list so it doesn't get forgotten!  I think I should make reference to that on the next schematic set.

More than one chip select would not be of any use unless a memory manufacturer decided to make a DRAM chip that passed through all the signals (and the additional chip select) to a package that sits above.

Theoretically it is possible, and there are examples of Package on Package on Package.  It's not uncommon for this to be done inside a single package (stacked die) but the interconnect is done usually with bond wires.

Unless we pass the 4-5 Million Pi's mark with no obvious tailing off of demand I think Broadcom would not be interested, I suspect the number is in reality much higher than this.  Making even a minor mod to silicon can cost millions of dollars.  One of the big costs used to be a mask set, but now I think direct imaging has taken this out of the loop. I'm sure there are people on the forum who could comment better than me - I just use the chips now. 

I used to make silicon but the advent of cheap (relatively) programmable logic (FPGAs)  has largely chopped away the mid volume market.  The stress of waiting for a PCB spin is nothing compared to 'first off' silicon - hats off to those guys, I'm to old to suffer that now!  You can fix a multitude of sins in an FPGA.

One option discussed before is to use a larger capacity POP memory chip but for the moment this is not in the roadmap.

Cheers

Pete

The engadget article I cited mentions getting 1GB by stacking 2 4Gb memory chips,

where otherwise stacking 4 2Gb chips would be required.  I'm not sure if that involves

multiple chip-select lines or not.  I'm also not certain what memory parts are actually

available since this article.

Looking at the article it looked like this is a stacked die ('chip') application inside a single package - should have made this clear in the previous post.  The BGA ball array is set up for Standard Mobile and not to sit on a POP architecture so I think we are out of luck here.

Pete

Even then...

It seems ARM code is pretty compact. I've compiled programs that seem to come out to 5 and 6k. That's nice.

Why do you NEED 1Gb of RAM?

A few weeks ago I was annoyed at my browser using over 1G of RAM. Then I calculated: It might cache a bitmap of that page for when I switch to that tab. I'd be annoyed if it would re-render it from the source if I switched tabs. If I Have 200 tabs open, a megapixel per page comes to 600 Mbytes.... A gig and a half isn't that bad for some overhead.

After loggin in a few times over the ethernet, I see the 'pi not touching the SD card to log me in. Everything needed has been cached. That's what it is supposed to be like.

Arduino-like board         raspberry pi.

16k flash.                     16G. (4G?)

2k? 4k? RAM                256M

serial 115k2                  USB 480Mbps

16x2 LCD on 8 pins       HDMI out / anallog video out.

No OS                          good OS.

To be able to run X I equipped my '486 machine with 8Mb instead of the standard 4Mb back in '91. A few years later, I had upgraded to 20 and then 32 Mb RAM and a new motherboard, I was swapping RAM modules around, and I thought my machine had crashed with the HDD led stuck on when the X weave showed up. Turns out the 32M was on the other motherboard I had forgotten to swap back: I was booting into X with 4Mb of memory. Things have bloated a bit. A kernel is now about 10x bigger than back then. A video card is no longer satisfied with "enough RAM to put the framebuffer in".

We've come a long way since then. The Raspberry pi is a nice machine with a whopping 256Mb of RAM. And because of the way it is built it can be sold cheap. And because of the way it's built, there is no system bus or memory slots. Tough luck.

Pete, While on the subject of RAM.... I've been running with a 208 / 48 split the last few days. How are my chances of running 240/16 ? I'm currently using a 656x416 framebuffer: No HDMI connected. Less than 300k pixels. i.e. a total of 1.2Mb for 32 bits per pixel (I can understand a GPU not supporting 24 BPP as it's a pain in the $%% (*))

(*) For the non-hardware guys, suppose you want to turn on the pixel at 101,101... Turns out that pixel is spread out over two 32-bit words. Really a mess to do.  Slows things down too. Best case, you have to do two writes to the framebuffer to turn on one pixel. Worst case you have to do two reads as well and delay those writes until you've gotten the results of those reads!

P.S. Look at: http://www.hynix.com/gl/products/mobile/mobile_info3.jsp

You can see there that they have up to 2Gbit of POP memory. About two years from now they will have 8Gbit and we can upgrade our 'pi to 1Gbyte of RAM.

Roger,

   you ask "why do you NEED 1GB of RAM?", especially when ARM code is

relatively compact.

   First, the compactness of code has almost nothing to do with RAM usage.

Most RAM is used by the data an application is processing, not the code of

the application.

   There are many reasons why 1GB+ of RAM is needed, although certainly

everyone's milage will differ.

   Most Linux distros currently have stated memory requirements of around 1GB,

especially for non-command-line usage.

   Most PC's currently come with 4GB+ of RAM, and many applications are

taking advantage of that memory, including IDE's like Eclipse, word processors

such as LibreOffice, GUI's such as Gnome, multi-tabbed browsers, etc.

  Compiling large linux packages takes over 1GB, including webkit, gtk,

LibreOffice.  Some linux distros depend on packages being compiled

natively rather than cross compiled.

  RAM can be used for I/O buffers, and for ramdisk, to compensate for

slow disk access.  The RPi forum is hosted on a machine with 96GB

of ram for that purpose.

p.s.

  8Gb lpddr2 memory chips appear to be available today, although

not certain at what price, quantity, and form factor.

see http://sunrisenanotech.com/products06f.html

       http://www.dramexchange.com

You shouldn't host a popular website and forum on a raspberry pi.

The forum on raspberrypi.org is moving to phpbb instead of the wordpress thingy. Why? PHPBB is written more efficiently so that it will be able to handle increasing traffic.

Writing reasonably efficient code will allow you to do things with your 'pi that it was made for. You'll have to buy a bigger machine to do bigger things.

The fact that chips are listed does not mean that they are available. They often make nice pages advertizing new products cleverly hiding the fact that they are not available until 3Q2012. They hope you'll design with their component and only then find out that you can't buy them in quantity. That said, no 8Gb, 168 ball, 1.8V DDR2 is listed in the page you mentioned. (I don't know how likely it is that they would be compatible if it were listed). On the other site, I could not find any specs to see if it might be compatible.