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Is the Raspberry B+ GPIO passed through with the Cirrus Audio card?

gkzsolt

The previous Wolfson card has a 26 pin header with male pins to connect to the Raspberry GPIO header after pushed on top of it. Does the new audio card do the same for the 40 pin header? Sorry, but I cannot discern from the card images I have.

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  • There is a table in the user manual with the remaining I/O on the expansion header.

     

    image

  • in reply to fvan

    In this table (e), pins 16-20 are ALL described as "General Purpose Pin GPIO 3", which looks to me like a copy/paste error from the pin 15 description.

     

    It would be nicer if table (e) were to read:

     

    PinNameType

    Power

    Domain

    		Description
    17GPIO6_EXDigital In/Out0 - 3.3VRPI General Purpose Pin GPIO6 (RPI pin 31)
    18GPIO12_EXDigital In/Out0 - 3.3VRPI General Purpose Pin GPIO12 (RPI pin 32)
    19GPIO16_EXDigital In/Out0 - 3.3VRPI General Purpose Pin GPIO16 (RPI pin 36)
    20GPIO26_EXDigital In/Out0 - 3.3VRPI General Purpose Pin GPIO26 (RPI pin 37)

     

     

    However, there are discrepancies between this table (e) and the description within the schematic that need to be figured out.

     

    Pins 10 and 11 are flipped between the schematic and table (e). (In the schematic, pin 10 is listed as PDMOUT_DAT [3] while table (e) says pin 10 is SDA. And vice versa for pin 11.) Which is correct?

     

    In the schematic, pin 14 is listed as connected to "GPIO5_EX [7]", which SHOULD correspond to PI GPIO 5 (PI pin 29). However table (e) lists pin 14 as being GND. Which is correct?

     

    In the Cirrus Logic Audio Card Comparison Table, it says that there are 8 PI connections (including the UART). The UART is connected to the Cirrus J8 Header. (RPI pins 8&10)

     

    Can anyone confirm definitively which are the other two GPIO pins that are tied directly from the PI into the Cirrus expansion header?

     

    • Expansion header pin 15 and 16 are marked GPIO4 and GPIO3, but those appear to be connected to GPIO4&3 on the WM5102_CSP137 chip instead of the RPi GPIO pins.
    • Pin 14 might be one of them if the schematic is correct but table e is not.

     

    Any definitive clues?

  • in reply to tonyhansen

    Good call. I've seen only now the whole schematics, sorry.

  • in reply to tonyhansen

    Yes, some of these errors I pointed out too in my comments to the CL manual.

     

    Pin 14 is GPIO 5 for sure. It is wired physically to the Pin 29 in 40-pin header.

     

    Pin 11 (Not Pin 10!) is wired to the Pin 03 of 40-pin header - GPIO 2 (SDA1, I2C). So, Pin 10 could be PDMDAT.

     

    As far as Pin 09 is SCL, and (I checked) it is connected to the Pin 05 of 40-pin header - it's GPIO 3. So the Pin 16 of Expansion header should be something else.

    Both of pins 15 and 16 are not connected to any of pins of 40-pin header.


    So we have 6 GPIOs that are tied directly from the RPI into the Cirrus L Expansion header (Pins 09, 11, 14, 17, 18, 19, 20).

    This is what can be easily verified by a simple multimeter.

     

     

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