The previous Wolfson card has a 26 pin header with male pins to connect to the Raspberry GPIO header after pushed on top of it. Does the new audio card do the same for the 40 pin header? Sorry, but I cannot discern from the card images I have.
The previous Wolfson card has a 26 pin header with male pins to connect to the Raspberry GPIO header after pushed on top of it. Does the new audio card do the same for the 40 pin header? Sorry, but I cannot discern from the card images I have.
In this table (e), pins 16-20 are ALL described as "General Purpose Pin GPIO 3", which looks to me like a copy/paste error from the pin 15 description.
It would be nicer if table (e) were to read:
| Pin | Name | Type | Power Domain | Description |
|---|---|---|---|---|
| 17 | GPIO6_EX | Digital In/Out | 0 - 3.3V | RPI General Purpose Pin GPIO6 (RPI pin 31) |
| 18 | GPIO12_EX | Digital In/Out | 0 - 3.3V | RPI General Purpose Pin GPIO12 (RPI pin 32) |
| 19 | GPIO16_EX | Digital In/Out | 0 - 3.3V | RPI General Purpose Pin GPIO16 (RPI pin 36) |
| 20 | GPIO26_EX | Digital In/Out | 0 - 3.3V | RPI General Purpose Pin GPIO26 (RPI pin 37) |
However, there are discrepancies between this table (e) and the description within the schematic that need to be figured out.
Pins 10 and 11 are flipped between the schematic and table (e). (In the schematic, pin 10 is listed as PDMOUT_DAT [3] while table (e) says pin 10 is SDA. And vice versa for pin 11.) Which is correct?
In the schematic, pin 14 is listed as connected to "GPIO5_EX [7]", which SHOULD correspond to PI GPIO 5 (PI pin 29). However table (e) lists pin 14 as being GND. Which is correct?
In the Cirrus Logic Audio Card Comparison Table, it says that there are 8 PI connections (including the UART). The UART is connected to the Cirrus J8 Header. (RPI pins 8&10)
Can anyone confirm definitively which are the other two GPIO pins that are tied directly from the PI into the Cirrus expansion header?
Any definitive clues?
For SPI, you're making a few assumptions:
Some people have played around with resoldering some of the audio card connectors to gain access to hidden pins like CLK, MOSI, and MISO. Feel free to try that and let us know how it goes.
With the Wolfson card, because of the P5 spring-loaded connector, there was little leeway to access the pins >from below< the audio card. But with the Cirrus Logic card, I don't see any reason that something like Element 14's RTC shim board wouldn't work.
So you MIGHT be able to do something similar to the shim board to access the CLK/MISO/MOSI pins. They MAY or may NOT work for you as SPI access. Go go for it and let us know what happens.
The thing to remember with the Wolfson and Cirrus Logic audio cards is that they were designed to take advantage of the RPi's capabilities to provide high-quality audio features. To do that, those cards use a LOT of the RPi's resources. Anything else we get to do with the RPi after that is a bonus. :-)
Hi Tony,
No, I am not making the assumption that the SPI bus pins are exposed. I know they are not, and that is what makes me wonder: why have the designers decided to hide them? In general, there should be no reason for that, except in some (unusual) cases.
In the schematics I see these 4 pins (MIS, MOSI, SCLK, SS) routed to the corresponding CIF2XX on the WM5102 chip (the RPI pins enter into IC U8, what seems to be a level shifter). From this I conclude that they are used for their purpose, in an SPI protocol and not been "reassigned to other uses", if you meant that. This also means that they can be used for other devices too (except SS). All SPI devices in a module share the same bus pins, ignoring them if their SS slave select pin is not active. So the question remains.
(I could go and try this with some experiments, but I don't have a Cirrus card yet. I am trying to figure out if it is worth buying one.)
May I ask if you could search through the "Cirrus Logic Audio Card User Manual.pdf"?
I agree very much with you in that a Cirrus card takes a lot of RPi's resources. But what worries me more, is the quality of documentation (very poor) and the lack of support. Is somebody at Cirrus reading and taking notice of these discussions? Or is there a place we can show some of these to a competent personnel (thinking of your table, etc.) ?
In Windows the pdf CLAC user manual also not text searchable (it searches only in small parts of text like tables and command examples).
Yes, and looks like there is nothing relevant to your question in the manual, any way.
Zsolt Gere Kiss wrote:
Hi Tony,
No, I am not making the assumption that the SPI bus pins are exposed. I know they are not, and that is what makes me wonder: why have the designers decided to hide them? In general, there should be no reason for that, except in some (unusual) cases.
In the schematics I see these 4 pins (MIS, MOSI, SCLK, SS) routed to the corresponding CIF2XX on the WM5102 chip (the RPI pins enter into IC U8, what seems to be a level shifter). From this I conclude that they are used for their purpose, in an SPI protocol and not been "reassigned to other uses", if you meant that. This also means that they can be used for other devices too (except SS). All SPI devices in a module share the same bus pins, ignoring them if their SS slave select pin is not active. So the question remains.
(I could go and try this with some experiments, but I don't have a Cirrus card yet. I am trying to figure out if it is worth buying one.)
May I ask if you could search through the "Cirrus Logic Audio Card User Manual.pdf"?
I agree very much with you in that a Cirrus card takes a lot of RPi's resources. But what worries me more, is the quality of documentation (very poor) and the lack of support. Is somebody at Cirrus reading and taking notice of these discussions? Or is there a place we can show some of these to a competent personnel (thinking of your table, etc.) ?
I cannot speak for the Wolfson designers - I don't know why they made some of their trade offs. I think they've heard loud and clear, though, that GPIO access is important to RPi designers.
However, their bottom line design rule appears to have been to provide access to a high-quality audio board. Everything else seemed to be secondary for them.
If that's your highest priority, as it was mine, then the answer is clear. If something else is more important, then your mileage will vary.
Searchability of PDF files is entirely dependent on the tools used when they are built. These do not appear to be searchable. But they are perfectly valid PDF files.
A number of people have asked similar questions to what you're asking. There's no consensus on any answers yet.
I have put together a complete table to capture the 26/40 way pins for the B and A+/B+ and the use of these pins on both the Wolfson and Cirrus cards. Hopefully this helps bring the information together and highlights the functions and availability of pins on the card. If there are any comments or feedback on the information please provide here, I think this will be useful based on the questions in the forum so I will pass the information on to E14 with the aim of adding to the user manual.
26/40 Way Pin allocation and function
| P1 Pin | Name | Model B | Model A+ /B+ | ||
| GPIO (BCM) | WAC Function | GPIO (BCM) | CLAC Function | ||
| 1 | 3V3 Power | ||||
| 2 | 5V0 Power | ||||
| 3 | SDA1 | GPIO2 | WM8804 I2C - SDA | GPIO2 | WM8804 I2C - SDA EXP/11 |
| 4 | 5V0 Power | ||||
| 5 | SCL1 | GPIO3 | WM8804 I2C - SCLK | GPIO3 | WM8804 I2C - SCLK EXP/9 |
| 6 | Ground | ||||
| 7 | GPIO_GCLK | GPIO4 | WM5102 MCLK2 (unused) WM8804 MCLK (unused) | GPIO4 | WM5102 MCLK2 (unused) WM8804 MCLK (unused) |
| 8 | TXD0 (UART) | GPIO14 | J8/1 | GPIO14 | J8/1 |
| 9 | Ground | ||||
| 10 | RXD0 (UART) | GPIO15 | J8/2 | GPIO15 | J8/2 |
| 11 | GPIO_GEN0 | GPIO17 | WM5102 RST | GPIO17 | WM5102 RST |
| 12 | GPIO_GEN1 (PCM_CLK) | GPIO18 | WM8804 - I2C Address Config | GPIO18 | WM5102 AIF PCM - BCLK |
| 13 | GPIO_GEN2 | GPIO27 | WM5102 IRQ | GPIO27 | WM5102 IRQ |
| 14 | Ground | ||||
| 15 | GPIO_GEN3 | GPIO22 | WM5102 LDO Enable | GPIO22 | WM5102 LDO Enable |
| 16 | GPIO_GEN4 | GPIO23 | WM8804 - Control I/F Config | GPIO23 | WM8804 - Control I/F Config |
| 17 | 3V3 Power | ||||
| 18 | GPIO_GEN5 | GPIO24 | WM5102 GPIO5 (unused) | GPIO24 | WM5102 GPIO5 (unused) |
| 19 | SPI_MOSI | GPIO10 | WM5102 SPI - MOSI | GPIO10 | WM5102 SPI - MOSI |
| 20 | Ground | ||||
| 21 | SPI_MISO | GPIO9 | WM5102 SPI - MISO | GPIO9 | WM5102 SPI - MISO |
| 22 | GPIO_GEN6 | GPIO25 | WM5102 GPIO3 (unused) EXP/16 | GPIO25 | WM5102 GPIO3 (unused) EXP/16 |
| 23 | SPI_SCLK | GPIO11 | WM5102 SPI - SCLK1 | GPIO11 | WM5102 SPI - SCLK1 |
| 24 | SPI_CE0_N | GPIO8 | WM8804 RST | GPIO8 | WM8804 RST |
| 25 | Ground | ||||
| 26 | SPI_CE1_N | GPIO7 | WM5102 SPI - CE | GPIO7 | WM5102 SPI - CE |
| 27 | ID_SD | GPIO0 | EEPROM | ||
| 28 | ID_SC | GPIO1 | EEPROM | ||
| 29 | GPIO5 | GPIO5 | EXP/14 | ||
| 30 | Ground | ||||
| 31 | GPIO6 | GPIO6 | EXP/17 | ||
| 32 | GPIO12 | GPIO12 | EXP/18 | ||
| 33 | GPIO13 | GPIO13 | WM8804 - I2C Address Config | ||
| 34 | Ground | ||||
| 35 | GPIO19 (PCM_FS) | GPIO19 | WM5102 AIF PCM - FS | ||
| 36 | GPIO16 | GPIO16 | EXP/19 | ||
| 37 | GPIO26 | GPIO26 | EXP/20 | ||
| 38 | GPIO20 (PCM_DIN) | GPIO20 | WM5102 AIF PCM - DIN | ||
| 39 | 3V3 Power | ||||
| 40 | GPIO21 (PCM_DOUT) | GPIO21 | WM5102 AIF PCM - DOUT | ||
| Note: Unused functions need to be treated carefully. Although they are not enabled in the current driver they provide scope for increased functionality going forward. | |||||
| P5 Connector (Model B Only) | ||
| Pin | Name | Model B |
| 1 | 5V0 Power | |
| 2 | 3V3 Power | |
| 3 | PCM_CLK | GPIO28 |
| 4 | PCM_FS | GPIO29 |
| 5 | PCM_DIN | GPIO30 |
| 6 | PCM_DOUT | GPIO31 |
| 7 | Ground | |
| 8 | Ground | |
Based on Tony's table of the 8 available GPIOs, I have updated this to include additional information. To clarify the 8 referenced available GPIO are numbers 6 to 13 in the table. I2C and SPI are functions utilised on the card so these can not be changed for other functions.
| | Cirrus Logic Audio Board Pin | RPi GPIO Description | RPI Alternate Description | RPi pin |
| 1 | EX 9 | GPIO 3 | SCL I2C | 5 |
| 2 | EX 11 | GPIO 2 | SDA1 I2C | 3 |
| 3 | J9-19 | GPIO 10 | SPI_MOSI | 19 |
| 4 | J9-21 | GPIO 9 | SPI_MISO | 21 |
| 5 | J9-23 | GPIO 11 | SPI_SCLK | 23 |
| 6 | EX 14 | GPIO 5 | 29 | |
| 7 | EX 16 | GPIO 25 | 22 | |
| 8 | EX 17 | GPIO 6 | 31 | |
| 9 | EX 18 | GPIO 12 | 32 | |
| 10 | EX 19 | GPIO 16 | 36 | |
| 11 | EX 20 | GPIO 26 | 37 | |
| 12 | J8-1 | GPIO 14 | UART TX | 8 |
| 13 | J8-2 | GPIO 15 | UART RX | 10 |
Thank you, Scott, it looks great and very helpful!
"Although they are not enabled in the current driver they provide scope for increased functionality going forward."
Does it mean I can use those "unused" GPIOs as is, or I need to hack kernel driver somehow to make them free for using?
> Does it mean I can use those "unused" GPIOs as is, or I need to hack kernel driver somehow to make them free for using?
I guess it means that you could use them now as is, if you'd want this very much, but you are not advised to do so, because they can be used some time in the future (drivers), for "increased functionality going forward" 
Scott, many thanks for this and for passing the information on to E14. Could you pls. correct "SCL I2C" in the table to "SCL1 I2C"? (there are 2 I2C interfaces on the RPi, and that is from intf. 1)
Also, if you could ask E14 to generate the doc pdf-s as for them to be searchable, it would be great. I don't think this to be too complicated, but the current manual is very, very hard to use. You cannot search any text, but neither can you copy and paste most of them, should it be a link, for example (text in tables *is* searchable, but normal text is not). I had to manually enter the (long) link from Annexe 7 d. of the "Schematic diagram" (have to enter this as well;), and on top of that, as I remember it was wrong, linking to the schematic of the Wolfson audio card! So please, can somebody at Cirrus check the links validity as well? Thanks,
Scott,
Your table suggests that the SPI control pins are still exposed through a header called J9. While this is good news, I am sorry to not find this header on the Cirrus schematics. Maybe I've missed it, but if not, would you be so kind to ask them for an update?
Thanks,
Zsolt
Scott,
Your table suggests that the SPI control pins are still exposed through a header called J9. While this is good news, I am sorry to not find this header on the Cirrus schematics. Maybe I've missed it, but if not, would you be so kind to ask them for an update?
Thanks,
Zsolt